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參數資料
| 型號： | ADF4360-2BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Integrated Synthesizer and VCO |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, QCC24 |
| 封裝： | 4 X 4 MM, MO-220-VGGD-2, LFCSP-24 |
| 文件頁數： | 18/20頁 |
| 文件大小： | 336K |
| 代理商： | ADF4360-2BCP |
PRELIMINARY TECHNICAL DATA
REV. PrA 07/03
–18–
0
P
ADF4360-2
INTERFACING
The ADF4360 family has a simple SPI-compatible serial
interface for writing to the device. CLK , DATA and LE
control the data transfer. When LE goes high the 24 bits
which have been clocked into the appropriate register on
each rising edge of CLK will get transferred to the
appropriate latch. See figure 1 for the Timing diagram and
Table I for the Latch Truth Table.
The maximum allowable serial clock rate is 20MHz. This
means the maximum update rate possible is 833kHz or one
update every 1.2 microseconds. This is certainly more than
adequate for systems that will have typical lock times in
hundreds of microseconds.
ADuC812 Interface
Figure 9
shows the interface between the ADF4360 family
and the ADuC812 microconverter. Since the ADuC812 is
based on an 8051 core, this interface can be used with any
8051-based microcontroller. The microconverter is setup for
SPI master mode with CPHA = 0. To initiate the operation,
the I/O port driving LE is brought low. Each latch of the
ADF4360 family is needs a 24-bit word. This is accomplished
by writing three 8-bit bytes from the microconverter to the
device. When the third byte has been written the LE input
should be brought high to complete the transfer.
POWER UP.
After power-up, the part needs a three writes for normal
operation. The correct sequence is to the R Counter latch,
followed by the Control latch
and finally the N Counter
latch.
ADSP-2181 Interface
Figure 10 shows the interface between the ADF4360 family
and the ADSP-21xx Digital Signal Processor. The ADF4360
family needs a 24-bit serial word for each latch write. The
easiest way to accomplish this is using the ADSP -21xx family
is to use the Autobuffered Transmit Mode of operation with
Alternate Framing. This provides a means for transmitting an
entire block of serial data before an interrupt is generated.
Set up the word length for 8 bits and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the 8-bit bytes, enable the Autobuffered mode and then
write to the the transmit register of the DSP. This last
operation initiates the autobuffer transfer.
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-24) are rectangular.
The printed circuit board pad for these should be 0.1mm
longer then the package land length and 0.05mm wider than
the package land width. The land should be centered on the
pad. This will ensure that the solder joint size is maximised.
The bottom of the chip scale package has a central thermal
pad. The thermal pad on the printed circuit board should be
at least as large as this exposed pad. On the printed curcuit
board, there should be a clearance of at least 0.25 mm
between the thermal pad and the inner edges of the pad
pattern. This will ensure that shorting is avoided.
Thermal vias may be used on the printed circuit board
thermal pad to improve thermal performance of the package.
If vias are used, they should be incorporated in the thermal
pad at 1.2mm pitch grid. The via diameter should be between
0.3mm and 0.33mm and the via barrel should be plated with
1oz copper to plug the via.
The user should connect the printed circuit thermal pad to
AGND. This is internally connected to AGND.
ADSP21XX
I/O Flags
{
ADF4360-x
SCLK
SDATA
LE
CE
MUXOUT
(Lock Detect)
SCLK
DT
TFS
ADuC812
ADF4360-x
SCLK
SDATA
LE
CE
MUXOUT
(Lock Detect)
SCLOCK
MOSI
I/O Ports
{
Figure 10. ADuC812 to ADF4360-x Interface
Figure 11. ADSP-21xx to ADF4360-x Interface
I/O port lines on the ADuC812 are also used to control
powerdown (CE input) and to detect lock (MUXOUT
configured as lock detect and polled by the port input).
When operating in the mode described, the maximum
SCLOCK rate of the ADuC812 is 4MHz. This means that the
maximum rate at which the output frequency can be changed
is 166kHz.
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| ADF4360-2BCPZRL | 功能描述:IC SYNTHESIZER VCO 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4360-2BCPZRL7 | 功能描述:IC SYNTHESIZER VCO 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數:1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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