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參數資料
| 型號： | ADF4360-8BCPRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Integrated Synthesizer and VCO |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, QCC24 |
| 封裝： | 4 X 4 MM, MO-220-VGGD-2, LFCSP-24 |
| 文件頁數： | 7/24頁 |
| 文件大?。?/td> | 539K |
| 代理商： | ADF4360-8BCPRL |
ADF4360-5
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
Rev. 0 | Page 7 of 24
ADF4360-5
TOP VIEW
(Not to Scale)
CPGND
1
AV
DD
AGND
2
3
RF
OUT
A
RF
OUT
B
V
VCO
4
5
6
DATA
18
CLK
17
REF
IN
DGND
16
15
C
N
R
SET
14
13
V
T
7
A
8
A
9
A
A
C
C
1
C
2
C
2
A
2
D
D
2
M
2
L
1
0
PIN 1
IDENTIFIER
Figure 3. Pin Configuration
Table 4. Pin Functional Descriptions
Pin No.
Mnemonic Function
1
CPGND
2
AV
DD
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AV
DD
must have the same value as DV
DD
.
Analog Ground. This is the ground return path of the prescaler and VCO.
VCO Output. The output level is programmable from 4.5 dBm to 13.5 dBm. See the Output Matching section
for a description of the various output stages.
VCO Complementary Output. The output level is programmable from 4.5 dBm to 13.5 dBm. See the Output
Matching section for a description of the various output stages.
Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. V
VCO
must have the same value as AV
DD
.
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP output voltage.
Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
Connecting a resistor between this pin and CP
GND
sets the maximum charge pump output current for the
synthesizer. The nominal voltage potential at the R
SET
pin is 0.6 V. The relationship between
I
CP
and
R
SET
is
75
.
11
=
3, 8–11, 22
4
AGND
RF
OUT
A
5
RF
OUT
B
6
V
VCO
7
12
13
V
TUNE
C
C
R
SET
SET
CPmax
R
I
Where
R
SET
= 4.7 k,
I
CPmax
= 2.5 mA.
Internal Compensation Node. This pin must be decoupled to V
VCO
with a 10 μF capacitor.
Digital Ground.
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input resistance of
100 k. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches, and the relevant latch is selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. DV
DD
must have the same value as AV
DD
.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
Taking the pin high powers up the device depending on the status of the power-down bits.
Charge Pump Output. When enabled, this provides ±
I
CP
to the external loop filter, which in turn drives the internal VCO.
14
15
16
C
N
DGND
REF
IN
17
CLK
18
DATA
19
LE
20
MUXOUT
21
DV
DD
23
CE
24
CP
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