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參數資料
| 型號： | ADM1020AR-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | 8-Lead, Low-Cost, System Temperature Monitor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數： | 2/12頁 |
| 文件大小： | 132K |
| 代理商： | ADM1020AR-REEL7 |
REV. 0
–2–
ADM1020–SPECIFICATIONS
(T
A
= T
MIN
to T
MAX
, V
DD
= 3.0 V to 3.6 V, unless otherwise noted)
Parameter
Min
Typ
Max
Units
Test Conditions/Comments
POWER SUPPLY AND ADC
Temperature Resolution
Temperature Error, Local Sensor
1
°
C
°
C
°
C
°
C
°
C
V
V
Guaranteed No Missed Codes
±
1
–3
–3
–5
3
2.5
+3
+3
+5
3.6
2.95
Temperature Error, Remote Sensor
T
A
= +60
°
C to +100
°
C
Supply Voltage Range
Undervoltage Lockout Threshold
Note 1
V
DD
Input, Disables ADC,
Rising Edge
2.7
Undervoltage Lockout Hysteresis
Power-On Reset Threshold
POR Threshold Hysteresis
Standby Supply Current
25
1.7
50
3
4
70
160
115
mV
V
mV
μ
A
μ
A
μ
A
μ
A
ms
0.9
2.2
V
DD
, Falling Edge
2
10
V
DD
= 3.3 V, No SMBus Activity
SCLK at 10 kHz
0.25 Conversions/Sec Rate
2 Conversions/Sec Rate
From Stop Bit to Conversion
Complete (Both Channels)
D+ Forced to D– + 0.65 V
High Level
Low Level
Average Operating Supply Current
Auto-Convert Mode, Averaged Over 4 Seconds
Conversion Time
190
290
170
65
Remote Sensor Source Current
90
5.5
0.7
50
μ
A
μ
A
V
μ
A
D– Source Voltage
Address Pin Bias Current
Momentary at Power-On Reset
SMBUS INTERFACE
Logic Input High Voltage, V
IH
STBY
, SCLK, SDATA
Logic Input Low Voltage, V
IL
STBY
, SCLK, SDATA
SMBus Output Low Sink Current
ALERT
Output Low Sink Current
Logic Input Current, I
IH
, I
IL
SMBus Input Capacitance, SCLK, SDATA
SMBus Clock Frequency
SMBus Clock Low Time, t
LOW
SMBus Clock High Time, t
HIGH
SMBus Start Condition Setup Time, t
SU:STA
SMBus Repeat Start Condition
Setup Time, t
SU:STA
SMBus Start Condition Hold Time, t
HD:STA
2.2
V
V
DD
= 3 V to 5.5 V
0.8
V
mA
mA
μ
A
pF
kHz
μ
s
μ
s
μ
s
ns
V
DD
= 3 V to 5.5 V
SDATA Forced to 0.6 V
ALERT
Forced to 0.4 V
6
1
–1
+1
5
0
4.7
4
4.7
250
100
t
LOW
Between 10% Points
t
HIGH
Between 90% Points
Between 90% and 90% Points
4
μ
s
Time from 10% of SDATA to
90% of SCLK
Time from 90% of SCLK to 10%
of SDATA
Time from 10% or 90% of
SDATA to 10% of SCLK
SMBus Stop Condition Setup Time, t
SU:STO
4
μ
s
SMBus Data Valid to SCLK
Rising Edge Time, t
SU:DAT
SMBus Data Hold Time, t
HD:DAT
SMBus Bus Free Time, t
BUF
SCLK Falling Edge to SDATA
Valid Time, t
VD,DAT
250
ns
0
4.7
μ
s
μ
s
Between Start/Stop Condition
1
μ
s
Master Clocking in Data
NOTES
1
Operation at V
= +5 V guaranteed by design, not production tested.
2
Guaranteed by design, not production tested.
Specifications subject to change without notice.
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