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參數資料
| 型號： | ADM1030ARQZ-RL7 |
| 廠商： | ON Semiconductor |
| 文件頁數： | 8/30頁 |
| 文件大小： | 327K |
| 描述： | IC SNSR TEMP/FAN PWM CTRL 16QSOP |
| 產品變化通告： | MFG CHG Notification ADI to ON Semi Product Obsolescence 11/Feb/2009 |
| 標準包裝： | 1,000 |
| 功能： | 風扇控制，溫度監控器 |
| 傳感器類型： | 內部和外部 |
| 感應溫度： | 0°C ~ 100°C，外部傳感器 |
| 精確度： | ±1°C，±1°C（最小值） |
| 拓撲： | ADC，比較器，多路復用器，寄存器庫 |
| 輸出類型： | SMBus? |
| 輸出警報： | 是 |
| 輸出風扇： | 是 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
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ADM1030
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8
during the high period, as a low-to-high transition
when the clock is high may be interpreted as a
STOP signal. The number of data bytes that can be
transmitted over the serial bus in a single READ or
WRITE operation is limited only by what the
master and slave devices can handle.
3. When all data bytes have been read or written,
stop conditions are established. In WRITE mode,
the master will pull the data line high during the
tenth clock pulse to assert a STOP condition. In
READ mode, the master device will override the
acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse.
This is known as No Acknowledge. The master
will then take the data line low during the low
period before the tenth clock pulse, then high
during the tenth clock pulse to assert a STOP
condition.
Any number of bytes of data may be transferred over the
serial bus in one operation, but it is not possible to mix read
and write in one operation, because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation.
In the case of the ADM1030, write operations contain
either one or two bytes, and read operations contain one
byte, and perform the following functions.
To write data to one of the device data registers or read
data from it, the Address Pointer Register must be set so that
the correct data register is addressed; data can then be
written into that register or read from it. The first byte of a
write operation always contains an address that is stored in
the Address Pointer Register. If data is to be written to the
device, then the write operation contains a second data byte
that is written to the register selected by the address pointer
register.
This is illustrated in Figure 15. The device address is sent
over the bus followed by R/W
set to 0. This is followed by
two data bytes. The first data byte is the address of the
internal data register to be written to, which is stored in the
Address Pointer Register. The second data byte is the data to
be written to the internal data register.
When reading data from a register there are two
possibilities:
1. If the ADM1030s Address Pointer Register value
is unknown or not the desired value, it is first
necessary to set it to the correct value before data
can be read from the desired data register. This is
done by performing a write to the ADM1030 as
before, but only the data byte containing the
register address is sent, as data is not to be written
to the register. This is shown in Figure 16.
A read operation is then performed consisting of
the serial bus address, R/W
bit set to 1, followed
by the data byte read from the data register. This is
shown in Figure 17.
2. If the Address Pointer Register is known to be
already at the desired address, data can be read
from the corresponding data register without first
writing to the Address Pointer Register, so
Figure 16 can be omitted.
NOTES:
1. Although it is possible to read a data byte from a data
register without first writing to the Address Pointer Register,
if the Address Pointer Register is already at the correct
value, it is not possible to write data to a register without
writing to the Address Pointer Register, because the first
data byte of a write is always written to the Address Pointer
Register.
2. In Figures 15 to 17, the serial bus address is shown as the
default value 01011(A1)(A0), where A1 and A0 are set by
the three-state ADD pin.
3. The ADM1030 also supports the Read Byte protocol, as
described in the System Management Bus specification.
Figure 15. Writing a Register Address to the Address Pointer Register,
then Writing Data to the Selected Register
R/W
0
SCL
SDA
1
0
1
1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADM1030
START BY
MASTER
1
9
1
ACK. BY
ADM1030
9
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADM1030
STOP BY
MASTER
1
9
SCL (CONTINUED)
SDA (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
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