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參數資料
| 型號： | ADM1033ARQ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | Thermal Monitor and Fan Speed (RPM) Controller |
| 中文描述： | DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 2Cel, RECTANGULAR, SURFACE MOUNT |
| 封裝： | MO-137AB, QSOP-16 |
| 文件頁數： | 22/40頁 |
| 文件大小： | 1164K |
| 代理商： | ADM1033ARQ-REEL7 |
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ADM1033
HANDLING SMBUSALERT INTERRUPTS
Rev. 0 | Page 22 of 40
To prevent tie-ups due to service interrupts, follow these steps:
1.
Detect an SMBus assertion.
2.
Enter the interrupt handler.
3.
Read the status register to identify the interrupt source.
4.
Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (Reg. 0x08 to Reg. 0x0A).
5.
Take the appropriate action for a given interrupt source.
6.
Exit the interrupt handler.
7.
Periodically poll the status register. If the interrupt status bit
has cleared, reset the corresponding interrupt mask bit to 0.
This causes the SMBusALERT output and status bits to
behave as shown in Figure 32.
TEMPERATURE
INTERRUPT MASK BIT
CLEARED
(SMBusALERT REARMED)
CLEARED ON READ
(TEMP BELOW LIMIT)
INTERRUPT
MASK BIT SET
HIGH LIMIT
SMBusALERT
"STICKY"
STATUS BIT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
0
Figure 32. Handling SMBusALERTs
INTERRUPT MASKING REGISTER
Mask Registers 1, 2, and 3 are located at Addresses 0x08, 0x09,
and 0x0A. These registers allow individual interrupt sources to
be masked out to prevent the ALERT interrupts. Note that
masking the interrupt source prevents only the ALERT from
being asserted; the appropriate status bit is set as normal.
Table 19. Mask Register 1 (Reg. 0x08)
Bit No.
Name
7
LH
Description
1 masks the ALERT for the local high
temperature.
1 masks the ALERT for the local low
temperature.
1 masks the ALERT for the remote high
temperature.
1 masks the ALERT for the remote low
temperature.
1 masks the ALERT for the remote diode
errors.
Reserved.
Reserved.
Reserved.
6
LL
5
RH
4
RL
3
RD
2
1
0
Table 20. Mask Register 2 (Reg. 0x09)
Bit No.
Name
7
Res
6
Res
5
Res
4
T%
Res
Res
Res
Description
Reserved.
Reserved.
Reserved.
1 masks the ALERT for the THERM timer
limit.
1 masks the ALERT for the THERM limit
being exceeded and the THERM output
signal being asserted.
1 masks the ALERT for a transition on
THERM; has no effect on ALERT in ALERT
Comp mode.
Reserved.
Reserved.
3
TA
2
TS
1
0
Res
Res
Table 21. Mask Register 3 (Reg. 0x0A)
Bit No.
Name
7
FS
6
FA
Description
1 masks the ALERT for fan stalling.
1 masks the ALERT for fan running at
ALARM speed.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
5
4
3
2
1
0
Res
Res
Res
Res
Res
Res
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