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參數資料
型號: ADM1041AARQZ-REEL
廠商: ANALOG DEVICES INC
元件分類: 通信及網絡
英文描述: Secondary-Side Controller with Current Share and Housekeeping
中文描述: SPECIALTY TELECOM CIRCUIT, PDSO24
封裝: LEAD FREE, MO-137AE, QSOP-24
文件頁數: 12/56頁
文件大小: 991K
代理商: ADM1041AARQZ-REEL
ADM1041A
Rev. 0 | Page 12 of 56
1
This specification is a measure of I
DD
during an EEPROM page erase cycle. The current is a dynamic. Refer to Figure 29 for a typical I
DD
plot during an EEPROM page
erase.
2
This specification is not production tested, but is supported by characterization data at initial product release.
3
Four external divider resistors are the same ratio, which is selected to produce 2.0 V nominal at Pin 21 while at zero load current. Recommended values are
3.3 V
5.0 V
12 V
R
TOP
680R
1K.5
5K1
R
BOTTOM
1K
1K
1K
4
Chopper off.
5
The maximum specification here is the maximum source current of Pin 8 as specified by the Absolute Maximum Ratings.
6
All internal amplifiers accept inputs with common range from GND to V
DD
2 V. The output is rail-to-rail, but the input is limited to GND to V
DD
2 V. See Figure 6.
7
These pins can be configured as open-drain N-channel or P-channel, (except PSON) and as normal or inverted logic polarity.
8
A logic true or false is defined strictly according to the signal name. Low and high refer to the pin or signal voltages.
9
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22, Method A117, and measured at 40°C, +25°C, and +85°C. Typical endurance at +25°C is 250,000 cycles.
10
Retention lifetime equivalent at junction temperature (T
J
) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 V.
Derates with junction temperature.
P
S
t
LOW
t
R
t
F
t
HD:STA
t
HD:DAT
t
SU:DAT
t
SU:STA
t
HD:STA
t
SU:STO
t
HIGH
SCL
P
S
SDA
t
BUF
0
Figure 5. Serial Bus Timing Diagram
SHRO
SHRS+
SHRS–
R1
R1
VB
VA
VB = V
DD
– 2V
R1 + R2
1k
Ω
VA = V
DD
– 0.4V
0
Figure 6. Amplifier Inputs and Outputs
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