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參數資料
| 型號： | ADM1069ACP-REEL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | SUPER SEQUENCER-TM WITH MARGINING CONTROL AND AUXILIARY ADC INPUTS |
| 中文描述： | 超時序與裕度控制以及輔助ADC輸入商標 |
| 文件頁數： | 7/32頁 |
| 文件大?。?/td> | 626K |
| 代理商： | ADM1069ACP-REEL |
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Preliminary Technical Data
ADM1069
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. PrB | Page 7 of 32
0
1
25
32
8
9
17
16
24
VX1
VX2
VX3
VX4
VP1
VP2
VP3
VH
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
G
V
S
S
A
A
V
P
A
R
R
R
D
D
D
D
PIN 1
ADM1069
TOP VIEW
(Not to Scale)
Figure 3. LQFP Pin Configuration
Table 2. Pin Function Descriptions
Pin
No.
Mnemonic
1–4
VX1–4
Description
High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to 1.375 V.
Alternatively, these pins can be used as general-purpose digital inputs.
Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation
on a potential divider connected to these pins, the output of which connects to a supply fault detector. These
pins allow thresholds from 2.5 V to 6.0 V, 1.25 V to 3.00 V, and 0.573 V to 1.375 V.
High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation
on a potential divider connected to this pin, the output of which connects to a supply fault detector. This pin
allows thresholds from 6.0 V to 14.4 V and 2.5 V to 6.0 V.
Ground Return for Input Attenuators.
Ground Return for On-Chip Reference Circuits.
Reference Input for ADC. Nominally, 2.048V.
2.048 V Reference Output.
Voltage Output DACs. These pins default to high impedance at power-up.
5–7
VP1–3
8
VH
9
10
11
12
13-
16
17-
24
25
26
27
28
29
30
31
32
AGND
REFGND
REFIN
REFOUT
DAC1-4
PDO8–1
Programmable Output Drivers.
PDOGND
VCCP
A0
A1
SCL
SDA
VDDCAP
GND
Ground Return for Output Drivers.
Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin and GND.
Logic Input. This pin sets the seventh bit of the SMBus interface address.
Logic Input. This pin sets the sixth bit of the SMBus interface address.
SMBus Clock Pin. Open-drain output requires external resistive pull-up.
SMBus Data I/O Pin. Open-drain output requires external resistive pull-up.
Device Supply Voltage. Linearly regulated from the highest of the VP1–3, VH pins to a typical of 4.75 V.
Supply Ground.
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