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參數資料
| 型號： | ADM4850AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 5 V Slew-Rate Limited Half- and Full-Duplex RS-485/RS-422 Transceivers |
| 中文描述： | LINE TRANSCEIVER, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁數： | 5/16頁 |
| 文件大?。?/td> | 438K |
| 代理商： | ADM4850AR |
ADM4850–ADM4857
ADM4852/ADM4856 TIMING SPECIFICATIONS
V = 5 V ± 5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 5.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay t
PLH
, t
PHL
Skew t
SKEW
Rise/Fall Time t
R
, t
F
Enable Time
Disable Time
Enable Time from Shutdown
RECEIVER
Propagation Delay t
PLH
, t
PHL
Differential Skew t
SKEW
Enable Time
Disable Time
Enable Time from Shutdown
Time to Shut Down
Rev. 0 | Page 5 of 16
Min
2.5
50
55
50
Typ
4000
5
20
4000
330
Max
180
50
140
180
180
190
50
50
50
3000
Unit
Mbps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
R
L
= 500 , C
L
= 100 pF, Figure 7, ADM4852
R
L
= 500 , C
L
= 15 pF, Figure 7, ADM4852
R
L
=500 , C
L
= 100 pF, Figure 7, ADM4852
C
L
= 15 pF, Figure 8
C
L
= 15 pF, Figure 8
R
L
= 1 k, C
L
= 15 pF, Figure 9, ADM4852
R
L
= 1 k, C
L
= 15 pF, Figure 9, ADM4852
R
L
= 1 k, C
L
= 15 pF, Figure 9, ADM4852
ADM4852
1
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4853/ADM4857 TIMING SPECIFICATIONS
V = 5 V ± 5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 6.
Parameter
Min
Typ
Max
DRIVER
Maximum Data Rate
10
Propagation Delay t
PLH
, t
PHL
0
30
Skew t
SKEW
10
Rise/Fall Time t
R
, t
F
30
Enable Time
35
Disable Time
35
Enable Time from Shutdown
4000
RECEIVER
Propagation Delay t
PLH
, t
PHL
55
190
Differential Skew t
SKEW
30
Enable Time
5
50
Disable Time
20
50
Enable Time from Shutdown
4000
Time to Shut Down
50
330
3000
Unit
Mbps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
R
LDIFF
= 54 , C
L1
= C
L2
= 100 pF, Figure 6
R
L
= 500 , C
L
= 100 pF, Figure 7, ADM4853
R
L
= 500 , C
L
= 15 pF, Figure 7, ADM4853
R
L
= 500 , C
L
= 100 pF, Figure 7, ADM4853
C
L
= 15 pF, Figure 8
C
L
= 15 pF, Figure 8
R
L
= 1 k, C
L
= 15 pF, Figure 9, ADM4853
R
L
= 1 k, C
L
= 15 pF, Figure 9, ADM4853
R
L
= 1 k, C
L
= 15 pF, Figure 9, ADM4853
ADM4853
1
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
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