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參數資料
| 型號： | ADM4850AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 5 V Slew-Rate Limited Half- and Full-Duplex RS-485/RS-422 Transceivers |
| 中文描述： | LINE TRANSCEIVER, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁數： | 7/16頁 |
| 文件大?。?/td> | 438K |
| 代理商： | ADM4850AR |
ADM4850–ADM4857
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 7 of 16
RO
1
V
CC
8
DI
4
GND
5
ADM4850/
ADM4851/
ADM4852/
ADM4853
TOP VIEW
(Not to Scale)
RE
2
B
7
0
DE
A
6
3
Figure 2. ADM4850–ADM4853 Pin Configuration
Table 8. ADM4850–ADM4853 Pin Descriptions
Pin No.
Mnemonic
1
RO
Description
Receiver Output. When enabled, if (AB) ≥ 30 mV, then RO = high.
If (AB) ≤ 200 mV, then RO = low.
Receiver Output Enable.
A low level enables the receiver output, RO.
A high level places it in a high impedance state.
Driver Output Enable. A high level enables the driver differential inputs A and B.
A low level places it in a high impedance state.
Driver Input. When the driver is enabled, a logic low on DI forces A low and B high,
while a logic high on DI forces A high and B low.
Ground.
Noninverting Receiver Input A/Driver Output A.
Inverting Receiver Input B/Driver Output B.
5 V Power Supply.
2
RE
3
DE
4
DI
5
6
7
8
GND
A
B
V
CC
V
CC
1
A
8
GND
4
Y
5
ADM4854/
ADM4855/
ADM4856/
ADM4857
TOP VIEW
(Not to Scale)
RO
2
B
7
0
DI
Z
6
3
Figure 3. ADM4854–ADM4857 Pin Configuration
Table 9. ADM4854–ADM4857 Pin Descriptions
Pin No.
1
2
Mnemonic
V
CC
RO
Description
5 V Power Supply.
Receiver Output. When enabled, if (AB) ≥ 30 mV, then RO = high.
If (AB) ≤ 200 mV, then RO = low.
Driver Input. When the driver is enabled, a logic low on DI forces Y low and Z high,
while a logic high on DI forces Y high and Z low.
Ground.
Driver Noninverting Output.
Driver Inverting Output.
Receiver Inverting Input.
Receiver Noninverting Input.
3
DI
4
5
6
7
8
GND
Y
Z
B
A
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