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參數資料
| 型號： | ADM695AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | Analog Switch / Multiplexer (Mux) IC; Analog Switch Function:High-Speed; Package/Case:16-SOIC; Leaded Process Compatible:Yes; Leakage Current:1nA; On Resistance, Rds(on):50ohm; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數： | 13/16頁 |
| 文件大小： | 284K |
| 代理商： | ADM695AR |
ADM690–ADM695
REV. A
–13–
ADM691
ADM693
ADM695
R
2
R
1
PFO
INPUT POWER
+5V
V
CC
V
BATT
V
OUT
CE
OUT
WDI
GND
PFI
0.1
μ
F
3V
BATTERY
RESET
0.1
μ
F
OSC IN
OSC SEL
LOW LINE
WDO
SYSTEM STATUS
INDICATORS
CMOS
RAM
ADDRESS
DECODE
I/O LINE
NMI
RESET
A0–A15
μ
P
0.1
μ
F
RESET
CE
IN
BATT
ON
NC
Figure 24. ADM691/ADM693/ADM695 Typical Application
Reset Output
T he internal voltage detector monitors V
CC
and generates a
RESET
output to hold the microprocessor’s Reset line low
when V
CC
is below 4.65 V (4.4 V for ADM693). An internal
timer holds
RESET
low for 50 ms (200 ms for the ADM695)
after V
CC
rises above 4.65 V (4.4 V for ADM693). T his prevents
repeated toggling of
RESET
even if the 5 V power drops out
and recovers with each power line cycle.
T he crystal oscillator normally used to generate the clock for mi-
croprocessors can take several milliseconds to stabilize. Since
most microprocessors need several clock cycles to reset,
RESET
must be held low until the microprocessor clock oscillator has
started. T he power-up
RESET
pulse lasts 50 ms (200 ms for the
ADM695) to allow for this oscillator start-up time. If a different
reset pulse width is required, then a capacitor should be con-
nected to OSC IN or an external clock may be used. Please refer
to T able I and Figure 4. T he manual reset switch and the 0.1
μ
F
capacitor connected to the reset line can be omitted if a manual
reset is not needed. An inverted, active high, RESET output is
also available.
Power Fail Detector
T he +5 V V
CC
power line is monitored via a resistive potential
divider connected to the Power Fail Input (PFI). When the
voltage at PFI falls below 1.3 V, the Power Fail Output (
PFO
)
drives the processor’s NMI input low. If for example a Power
Fail threshold of 4.8 V is set with resistors R
1
and R
2
, the micro-
processor will have the time when V
CC
falls from 4.8 V to 4.65 V
to save data into RAM. An earlier power fail warning can be
generated if the unregulated dc input to the 5 V regulator is
available for monitoring. T his will allow more time for micro-
processor housekeeping tasks to be completed before power is
lost.
RAM Write Protection
T he ADM691/ADM693/ADM695
CE
OUT
line drives the Chip
Select inputs of the CMOS RAM.
CE
OUT
follows
CE
IN
as long
as V
CC
is above the 4.65 V (4.4 V for ADM693) reset threshold.
If V
CC
falls below the reset threshold,
CE
OUT
goes high, inde-
pendent of the logic level at
CE
IN
. T his prevents the micropro-
cessor from writing erroneous data into RAM during power-up,
power-down, brownouts and momentary power interruptions.
Watchdog T imer
T he microprocessor drives the Watchdog Input (WDI) with an
I/O line. When OSC IN and OSC SEL are unconnected, the
microprocessor must toggle the WDI pin once every 1.6 sec-
onds to verify proper software execution. If a hardware or soft-
ware failure occurs such that WDI not toggled, the ADM691/
ADM693 will issue a 50 ms (200 ms for ADM695)
RESET
pulse after 1.6 seconds. T his typically restarts the micro-
processor’s power-up routine. A new
RESET
pulse is issued
every 1.6 seconds until WDI is again strobed. If a different
watchdog timeout period is required, then a capacitor should be
connected to OSC IN or an external clock may be used. Please
refer to T able I and Figure 4.
T he WAT CHDOG OUT PUT (
WDO
) goes low if the watch-
dog timer is not serviced within its timeout period. Once
WDO
goes low, it remains low until a transition occurs at WDI. T he
watchdog timer feature can be disabled by leaving WDI
unconnected.
T he
RESET
output has an internal 3
μ
A pull-up, and can either
connect to an open collector reset bus or directly drive a CMOS
gate without an external pull-up resistor.
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|---|---|
| ADM695SQ | Microprocessor Supervisory Circuits |
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| ADM695 | Microprocessor Supervisory Circuits(微處理器監控電路) |
| ADM690 | Microprocessor Supervisory Circuits(微處理器監控電路) |
| ADM696 | Microprocessor Supervisory Circuits(微處理器監控電路) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADM695AR-REEL | 功能描述:IC SUPERVISOR MPU 4.65V 16SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監控器 系列:- 標準包裝:400 系列:- 類型:備用電池電路 監視電壓數目:1 輸出:開路漏極，推挽式 復位:高有效/低有效 復位超時:最小為 35 ms 電壓 - 閥值:4.65V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:16-SOIC W 包裝:帶卷 (TR) 其它名稱:ADM691ARZ-REEL7TR |
| ADM695ARZ | 功能描述:IC SUPER MPU 4.65 100MA 16SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 監控器 系列:- 標準包裝:100 系列:- 類型:簡單復位/加電復位 監視電壓數目:1 輸出:開路漏極，開路漏極 復位:高有效/低有效 復位超時:最小為 250 ms 電壓 - 閥值:4.37V，4.62V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOIC 包裝:管件 產品目錄頁面:1337 (CN2011-ZH PDF) |
| ADM695ARZ | 制造商:Analog Devices 功能描述:IC SUPERVISORY CIRCUIT |
| ADM695ARZ-REEL | 功能描述:IC SUPERVISOR MPU 4.65V 16SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 監控器 系列:- 標準包裝:400 系列:- 類型:備用電池電路 監視電壓數目:1 輸出:開路漏極，推挽式 復位:高有效/低有效 復位超時:最小為 35 ms 電壓 - 閥值:4.65V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:16-SOIC W 包裝:帶卷 (TR) 其它名稱:ADM691ARZ-REEL7TR |
| ADM695SQ | 功能描述:IC SUPERVISOR MPU 4.65V 16CDIP RoHS:否 類別:集成電路 (IC) >> PMIC - 監控器 系列:- 標準包裝:1 系列:- 類型:簡單復位/加電復位 監視電壓數目:1 輸出:開路漏極或開路集電極 復位:高有效 復位超時:- 電壓 - 閥值:1.8V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:6-TSOP（0.059"，1.50mm 寬）5 引線 供應商設備封裝:5-TSOP 包裝:剪切帶 (CT) 其它名稱:NCP301HSN18T1GOSCT |
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