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參數資料
| 型號： | ADM697 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Microprocessor Supervisory Circuits(微處理器監控電路) |
| 中文描述： | 微處理器監控電路（微處理器監控電路） |
| 文件頁數： | 5/12頁 |
| 文件大小： | 359K |
| 代理商： | ADM697 |
ADM696/ADM697
REV. 0
–5–
Low Line
RESE
T OUTPUT
RESET
is an active low output which provides a
RESET
signal
to the microprocessor whenever the Low Line Input (LL
IN
) is
below 1.3 V. The LL
IN
input is normally used to monitor the
power supply voltage. An internal timer holds
RESET
low for
50 ms after the voltage on LL
IN
rises above 1.3 V. This is in-
tended as a power-on
RESET
signal for the processor. It allows
time for the power supply and microprocessor to stabilize. On
power-down, the
RESET
output remains low with V
CC
as low
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition.
The LL
IN
comparator has approximately 12 mV of hysteresis
for enhanced noise immunity.
In addition to
RESET
, an active high RESET output is also
available. This is the complement of
RESET
and is useful for
processors requiring an active high RESET.
t
1
t
1
= RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
V2
V2
V1
V1
t
1
LL
IN
LOW LINE
RESET
Figure 2. Power-Fail Reset Timing
Watchdog Timer
RESET
The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within
the selected timeout period, a
RESET
pulse is generated. The
ADM696/ADM697 may be configured for either a fixed
“short” 100 ms or a “long” 1.6 second timeout period or for an
adjustable timeout period. If the “short” period is selected some
systems may be unable to service the watchdog timer immedi-
ately after a reset, so a “long” timeout is automatically initiated
directly after a reset is issued. The watchdog timer is restarted
at the end of Reset, whether the Reset was caused by lack of ac-
tivity on WDI or by LL
IN
falling below the reset threshold.
The normal (short) timeout period becomes effective following
the first transition of WDI after
RESET
has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be is-
sued after each timeout period (1.6 s). The watchdog monitor
can be deactivated by floating the Watchdog Input (WDI) or by
connecting it to midsupply.
CIRCUIT INFORMATION
Battery-Switchover Section (ADM696)
The battery switchover circuit compares V
CC
to the V
BATT
input, and connects V
OUT
to whichever is higher. Switchover
occurs when V
CC
is 50 mV higher than V
BATT
as V
CC
falls, and
when V
CC
is 70 mV greater than V
BATT
as V
CC
rises. This
20 mV of hysteresis prevents repeated rapid switching if V
CC
falls very slowly or remains nearly equal to the battery voltage.
During normal operation with V
CC
higher than V
BATT
, V
CC
is
internally switched to V
OUT
via an internal PMOS transistor
switch. This switch has a typical on resistance of 1.5
and can
supply up to 100 mA at the V
OUT
terminal. V
OUT
is normally
used to drive a RAM memory bank which may require instanta-
neous currents of greater than 100 mA. If this is the case, then
a bypass capacitor should be connected to V
OUT
. The capacitor
will provide the peak current transients to the RAM. A capaci-
tance value of 0.1
μ
F or greater may be used.
If the continuous output current requirement at V
OUT
exceeds
100 mA or if a lower V
CC
–V
OUT
voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output can directly
drive the base of the external transistor.
A 20
MOSFET switch connects the V
BATT
input to V
OUT
during battery backup. This MOSFET has very low input-to-
output differential (dropout voltage) at the low current levels
required for battery backup of CMOS RAM or other low power
CMOS circuitry. The supply current in battery backup is typi-
cally 0.6
μ
A.
The ADM696 operates with battery voltages from 2.0 V to V
CC
–0.3 V). High value capacitors, either standard electrolytic or
the farad-size double layer capacitors, can also be used for short-
term memory backup. A small charging current of typically
10 nA (0.1
μ
A max) flows out of the V
BATT
terminal. This cur-
rent is useful for maintaining rechargeable batteries in a fully
charged condition. This extends the life of the backup battery
by compensating for its self discharge current. Also note that
this current poses no problem when lithium batteries are used
for backup since the maximum charging current (0.1
μ
A) is safe
for even the smallest lithium cells.
If the battery-switchover section is not used, V
BATT
should be
connected to GND and V
OUT
should be connected to V
CC
.
V
BATT
V
CC
BATT ON
(ADM691, ADM693,
ADM695, ADM696)
V
OUT
700
mV
GATE DRIVE
100
mV
INTERNAL
SHUT DOWN SIGNAL
WHEN
V
BATT
> (V
CC
+ 0.7V)
Figure 1. Battery Switchover Schematic
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| ADM697AN | 功能描述:IC SUPERVISOR MPU 100MA 16DIP RoHS:否 類別:集成電路 (IC) >> PMIC - 監控器 系列:- 標準包裝:1 系列:- 類型:簡單復位/加電復位 監視電壓數目:1 輸出:開路漏極或開路集電極 復位:高有效 復位超時:- 電壓 - 閥值:1.8V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:6-TSOP（0.059"，1.50mm 寬）5 引線 供應商設備封裝:5-TSOP 包裝:剪切帶 (CT) 其它名稱:NCP301HSN18T1GOSCT |
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