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參數資料
| 型號： | ADM8693ARN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | Thyristor Module; Current, It av:250A; Repetitive Reverse Voltage Max, Vrrm:1600V; Peak Surge Current:8800A; di/dt:800A/ s; Package/Case:ND44; Peak Reflow Compatible (260 C):Yes; Current Rating:250A |
| 中文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16 |
| 封裝： | MS-012AC, SOIC-16 |
| 文件頁數： | 10/16頁 |
| 文件大小： | 207K |
| 代理商： | ADM8693ARN |
ADM8690–ADM8695
REV. 0
–10–
+APPLICAT ION INFORMAT ION
Increasing the Drive Current
If the continuous output current requirements at V
OUT
exceed
100 mA, or if a lower V
CC
–V
OUT
voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. T he BAT T ON output (ADM8691/
ADM8693/ADM8695) can directly drive the base of the exter-
nal transistor.
PNP TRANSISTOR
0.1μF
0.1μF
BATTERY
+5V INPUT
POWER
V
CC
BATT
ON
V
OUT
V
BATT
ADM8691
ADM8693
ADM8695
Figure 17. Increasing the Drive Current
Using a Rechargeable Battery for Backup
If a capacitor or a rechargeable battery is used for backup then
the charging resistor should be connected to V
OUT
since this
eliminates the discharge path that would exist during power-
down if the resistor is connected to V
CC
.
0.1μF
0.1μF
RECHARGEABLE
BATTERY
+5V INPUT
POWER
V
CC
V
OUT
V
BATT
ADM869x
R
I =
V
OUT
– V
BATT
R
Figure 18. Rechargeable Battery
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is nonin-
verting, hysteresis can be added simply by connecting a resistor be-
tween the
PFO
output and the PFI input as shown in Figure 19.
When
PFO
is low, resistor R
3
sinks current from the summing
junction at the PFI pin. When
PFO
is high, the series combina-
tion of R3 and R4 source current into the PFI summing junc-
tion. T his results in differing trip levels for the comparator.
ADM869x
1.3V
PFI
PFO
R
1
R
2
+7V TO +15V
INPUT
POWER
R
4
R
3
V
CC
TO μP NMI
+5V
7805
5V
0V
PFO
0V
V
L
V
H
V
IN
V
H
= 1.3V
(
1+ R
)
V
L
= 1.3V
(
1+ R
)
2
ASSUMING R
4
< < R
3
THEN
1
R
2
R
1
R
3
R
1
R
1
(5V – 1.3V)
1.3V (R
3
+ R
4
)
R
1
R
2
HYSTERESIS V
H
– V
L
= 5V
(
)
Figure 19. Adding Hysteresis to the Power Fail Comparator
Monitoring the Status of the Battery
T he power fail comparator can be used to monitor the status of
the backup battery instead of the power supply if desired. T his
is shown in Figure 20. T he PFI input samples the battery volt-
age and generates an active low
PFO
signal when the battery
voltage drops below a chosen threshold. It may be necessary to
apply a test load in order to determine the loaded battery volt-
age. T his can be done under processor control using
CE
OUT .
Since
CE
OUT
is forced high during the battery backup mode, the
test load will not be applied to the battery while it is in use, even
if the microprocessor is not powered.
ADM869x
PFO
+5V INPUT
POWER
CE
IN
CE
OUT
PFI
V
BATT
V
CC
BATTERY
20k
OPTIONAL
TEST LOAD
10M
10M
LOW BATTERY
SIGNAL TO
μP I/O PIN
FROM μP I/O PIN
APPLIES TEST LOAD
TO BATTERY
Figure 20. Monitoring the Battery Status
Alternate Watchdog Input Drive Circuits
T he watchdog feature can be enabled and disabled under pro-
gram control by driving WDI with a three-state buffer (Figure
21a). When three-stated, the WDI input will float, thereby dis-
abling the watchdog timer.
WDI
ADM869x
WATCHDOG
STROBE
CONTROL
INPUT
Figure 21a. Programming the Watchdog Input
T his circuit is not entirely foolproof, and it is possible that a
software fault could erroneously three-state the buffer. T his
would then prevent the ADM869x from detecting that the mi-
croprocessor is no longer operating correctly. In most cases a
better method is to extend the watchdog period rather than dis-
abling the watchdog. T his may be done under program control
using the circuit shown in Figure 21b. When the control input is
high, the OSC SEL pin is low and the watchdog timeout is set
by the external capacitor. A 0.01
μ
F capacitor sets a watchdog
timeout delay of 100 seconds. When the control input is low,
the OSC SEL pin is driven high, selecting the internal oscillator.
T he 100 ms or the 1.6 s period is chosen, depending on which di-
ode in Figure 21b is used. With D1 inserted, the internal timeout is
set at 100 ms; with D2 inserted the timeout is set at 1.6 s.
D2
D1
CONTROL
INPUT*
ADM869x
OSC SEL
OSC IN
*LOW = INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT
Figure 21b. Programming the Watchdog Input
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