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| 型號(hào)： | ADN2806ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/20頁 |
| 文件大小： | 0K |
| 描述： | IC CLK/DATA REC 622MBPS 32-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | CML |
| 輸出： | LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
622 Mbps Clock and Data Recovery IC
Data Sheet
ADN2806
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2006–2012 Analog Devices, Inc. All rights reserved.
FEATURES
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Patented clock recovery architecture
No reference clock required
Loss-of-lock indicator
I2C interface to access optional features
Single-supply operation: 3.3 V
Low power: 359 mW typical
5 mm × 5 mm, 32-lead LFCSP, Pb free
APPLICATIONS
BPON ONT
SONET OC-12
WDM transponders
Regenerators/repeaters
Test equipment
Broadband cross-connects and routers
GENERAL DESCRIPTION
The ADN2806 provides the receiver functions for clock and
data recovery, and data retiming for 622 Mbps NRZ data. The
ADN2806 automatically locks to 622 Mbps data without the
need for an external reference clock or programming. All
SONET jitter requirements are met, including jitter transfer,
jitter generation, and jitter tolerance. All specifications are
quoted for 40°C to +85°C ambient temperature, unless
otherwise noted.
This device, together with a PIN diode, TIA preamplifier, and a
lim amp can implement a highly integrated, low cost, low power
fiber optic receiver.
The ADN2806 is available in a compact 5 mm × 5 mm,
32-lead LFCSP.
FUNCTIONAL BLOCK DIAGRAM
2
LOL
DATAOUTP/
DATAOUTN
CLKOUTP/
CLKOUTN
ADN2806
2
VCC
VEE
CF1
CF2
PIN
NIN
VREF
BUFFER
VCO
PHASE
SHIFTER
PHASE
DETECT
FREQUENCY
DETECT
DATA
RE-TIMING
LOOP
FILTER
LOOP
FILTER
REFCLKP/REFCLKN
(OPTIONAL)
0
58
31
-0
01
Figure 1.
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| ADN2806ACPZ-500RL7 | 功能描述:IC CLK/DATA REC 622MBPS 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ADN2806ACPZ-RL7 | 功能描述:IC CLK/DATA REC 622MBPS 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ADN2807 | 制造商:AD 制造商全稱:Analog Devices 功能描述:155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2807ACP | 制造商:Analog Devices 功能描述:CDR 155.52Mbps/166.63Mbps/622.08Mbps/666.51Mbps SONET/SDH 48-Pin LFCSP EP Tray |
| ADN2807ACP-RL | 制造商:AD 制造商全稱:Analog Devices 功能描述:155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp |
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