- 您現在的位置：買賣IC網 > PDF目錄374016 > ADN2812 (Analog Devices, Inc.) Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp PDF資料下載
參數資料
| 型號： | ADN2812 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | 連續速率12.3 Mb / s的2.7 Gb / s的集成時鐘和數據恢復芯片限幅放大器 |
| 文件頁數： | 8/28頁 |
| 文件大小： | 478K |
| 代理商： | ADN2812 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
ADN2812
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 8 of 28
0
TEST1 1
VCC 2
VREF 3
NIN 4
PIN 5
SLICEP 6
SLICEN 7
VEE 8
PIN 1
TOP VIEW
(Not to Scale)
24 VCC
23 VEE
22 LOS
21 SDA
20 SCK
19 SADDR5
18 VCC
17 VEE
3
T
R
R
V
V
C
C
L
3
3
2
2
2
2
2
ADN2812*
*THERE IS AN EXPOSED PAD ON THE BOTTOM OF
THE PACKAGE THAT MUST BE CONNECTED TO GND.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
1
TEST1
2
VCC
3
VREF
4
NIN
5
PIN
6
SLICEP
7
SLICEN
8
VEE
9
THRADJ
10
REFCLKP
11
REFCLKN
12
VCC
13
VEE
14
CF2
15
CF1
16
LOL
17
VEE
18
VCC
19
SADDR5
20
SCK
21
SDA
22
LOS
23
VEE
24
VCC
25
CLKOUTN
26
CLKOUTP
27
SQUELCH
28
DATAOUTN
29
DATAOUTP
30
VEE
31
VCC
32
TEST2
Exposed Pad
Pad
Type
1
P
AO
AI
AI
AI
AI
P
AI
DI
DI
P
P
AO
AO
DO
P
P
DI
DI
DI
DO
P
P
DO
DO
DI
DO
DO
P
P
P
Description
Connect to VCC.
Power for Limamp, LOS.
Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor.
Differential Data Input. CML.
Differential Data Input. CML.
Differential Slice Level Adjust Input.
Differential Slice Level Adjust Input.
GND for Limamp, LOS.
LOS Threshold Setting Resistor.
Differential REFCLK Input. 12.3 MHz to 200 MHz.
Differential REFCLK Input. 12.3 MHz to 200 MHz.
VCO Power.
VCO GND.
Frequency Loop Capacitor.
Frequency Loop Capacitor.
Loss of Lock Indicator. LVTTL active high.
FLL Detector GND.
FLL Detector Power.
Slave Address Bit 5.
I
2
C Clock Input.
I
2
C Data Input.
Loss of Signal Detect Output. Active high. LVTTL.
Output Buffer, I
2
C GND.
Output Buffer, I
2
C Power.
Differential Recovered Clock Output. CML.
Differential Recovered Clock Output. CML.
Disable Clock and Data Outputs. Active high. LVTLL.
Differential Recovered Data Output. CML.
Differential Recovered Data Output. CML.
Phase Detector, Phase Shifter GND.
Phase Detector, Phase Shifter Power.
Connect to VCC.
Connect to GND
1
Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.
相關PDF資料 |
PDF描述 |
|---|---|
| ADN2812ACP | Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2812ACP-RL | Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2812ACP-RL7 | Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2819 | Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2819ACP-CML | Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADN2812ACP | 制造商:Analog Devices 功能描述:IC CLOCK/DATA RECOVERY |
| ADN2812ACP-RL | 制造商:Analog Devices 功能描述:Clock and Data Recovery 32-Pin LFCSP EP T/R |
| ADN2812ACP-RL7 | 制造商:Analog Devices 功能描述:Clock and Data Recovery 32-Pin LFCSP EP T/R |
| ADN2812ACPZ | 功能描述:IC CLOCK/DATA RECOVERY 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1 系列:- 類型:時鐘/頻率發生器，多路復用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| ADN2812ACPZ-RL | 功能描述:IC CLOCK/DATA RECOVERY 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
發布緊急采購，3分鐘左右您將得到回復。