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參數資料
| 型號： | ADN2850ACP250 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字電位計 |
| 英文描述： | TERM,RING NON-INSUL. |
| 中文描述： | DUAL 250K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, QCC16 |
| 封裝： | 5 X 5 MM, LFCSP-16 |
| 文件頁數： | 7/18頁 |
| 文件大?。?/td> | 270K |
| 代理商： | ADN2850ACP250 |
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Programmable Resistors
ADN2850
REV PrH, 13, AUG 2001
7
Table 1. ADN2850 24-bit Serial Data Word
MSB
RDAC
C3
C2
C1
EEMEM
C3
C2
C1
LSB
D0
D0
C0
C0
0
A3
0
A2
0
A1
A0
A0
X
D
15
X
D
14
X
D
13
X
D
12
X
D
11
X
D
10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
Command bits are C0 to C3. Address bits are A3-A0. Data bits D0 to D9 are applicable to RDAC whereas D0 to D15 are applicable to EEMEM Command
instruction codes are defined in table 2.
Table 2. ADN2850 Instruction/Operation Truth Table
a,b,d
Inst
No.
B23 B16
C3 C2 C1 C0 A3 A2 A1 A0
0
0 0 0 0 X X X X
Instruction Byte 0
Data Byte 1
B15
B8
X D9 D8
X X X
Data Byte 0
B7 B0
Operation
D7 D0
X X
NOP: Do nothing
1
0 0 0 1 0 0 0 A0
X X X
X X
Write contents of EEMEM(A0) to RDAC(A0)
Register). This command leaves device in the Read
Programpower state. To return part to the idle
state, performNOP instruction #0
SAVE WIPER SETTING: Write contents of
RDAC(A0) to EEMEM(A0)
Write contents of Serial Register Data Bytes 0 & 1
to EEMEM(ADDR)
Decrement 6dB: Right Shift contents of RDAC(A0),
steops at all “Zeros”.
Decrement All 6dB: Right Shift contents of all
RDAC Registers, stops at all “Zeros”.
Decrement contents of RDAC(A0) by “One”, stops
at all “Zero”.
Decrement contents of all RDAC Register by “One”,
stops at all “Zero”.
RESET: Load all RDACs with their corresponding
EEMEMpreviously-saved values
Write contents of EEMEM(ADDR) to Serial Register
Data Bytes 0 & 1. SDO activated. See Figure xxxx
Write contents of RDAC(A0) to Serial Register Data
Bytes 0 & 1. SDO activated. See Figure xxxx
Write contents of Serial Register Data Bytes 0 &1
to RDAC(A0)
Increment 6dB: Left Shift contents of RDAC(A0),
stops at all “Ones”.
Increment All 6dB: Left Shift contents of all RDAC
Registers, stops at all “Ones”.
Increment contents of RDAC(A0) by “One”, stops at
all “Ones”.
Increment contents of all RDAC Register by “One”,
stops at all “Ones”.
2
0 0 1 0 0 0 0 A0
X X X
X X
3
e
0 0 1 1 << ADDR >>
D15 D8
D7 D0
4
c
0 1 0 0 0 0 0 A0
X X X
X X
5
c
0 1 0 1 X X X X
X X X
X X
6
c
0 1 1 0 0 0 0 A0
X X X
X X
7
c
0 1 1 1 X X X X
X X X
X X
8
1 0 0 0 0 0 0 0
X X X
X X
9
1 0 0 1 << ADDR >>
X X X
X X
10
1 0 1 0 0 0 0 A0
X X X
X X
11
1 0 1 1 0 0 0 A0
X D9 D8
D7 D0
12
c
1 1 0 0 0 0 0 A0
X X X
X X
13
c
1 1 0 1 X X X X
X X X
X X
14
c
1 1 1 0 0 0 0 A0
X X X
X X
15
c
1 1 1 1 X X X X
X X X
X X
NOTES:
a)
The SDO output shifts-out the last 24-bits of data clocked into the serial register for daisy chain operation. Exception, following Instruction #9 or #10
the selected internal register data will be present in data byte 0 & 1. Instructions following #9 & #10 must be a full 24-bit data word to completely
clock out the contents of the serial register.
The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding non-volatile EEMEM register.
The increment, decrement and shift commands ignore the contents of the shift register Data Bytes 0 and 1.
Execution of the above Operations takes place when the
CS
strobe returns to logic high.
Instruction #3 write two data bytes to EEMEM. But in the cases of addresses 0 and 1, only the last 10 bits are valid for wiper position setting.
b)
c)
d)
e)
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