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參數資料
| 型號： | ADP2140ACPZ3328R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 20/32頁 |
| 文件大小： | 2731K |
| 描述： | IC REG DL BCK/LINEAR 10LFCSP |
| 標準包裝： | 1 |
| 拓撲： | 降壓（降壓）同步（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數： | 2 |
| 頻率 - 開關： | 3MHz |
| 電壓/電流 - 輸出 1： | 3.3V，600mA |
| 電壓/電流 - 輸出 2： | 2.8V，300mA |
| 帶 LED 驅動器： | 無 |
| 帶監控器： | 無 |
| 帶序列發生器： | 是 |
| 電源電壓： | 1.65 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤，CSP |
| 供應商設備封裝： | 10-LFCSP-WD（3x3） |
| 包裝： | 標準包裝 |
| 其它名稱： | ADP2140ACPZ3328R7DKR |
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ADP2140
Data Sheet
Rev. A | Page 20 of 32
SELECTED FEATURES
SHORT-CIRCUIT PROTECTION
The ADP2140 includes frequency foldback to prevent output
current runaway on a hard short. When the voltage at the feed-
back pin falls below 50% of the nominal output voltage, indicating
the possibility of a hard short at the output, the switching frequency
is reduced to 1/2 of the internal oscillator frequency. The reduc-
tion in the switching frequency gives more time for the inductor
to discharge, preventing a runaway of output current.
UNDERVOLTAGE LOCKOUT
To protect against battery discharge, undervoltage lockout
circuitry is integrated on the ADP2140. If the input voltage
drops below the 2.15 V UVLO threshold, the ADP2140 shuts
down and both the power switch and synchronous rectifier turn
off. When the voltage rises again above the UVLO threshold,
the soft start period initiates and the part is enabled.
THERMAL PROTECTION
In the event that the ADP2140 junction temperatures rises above
150癈, the thermal shutdown circuit turns off the converter.
Extreme junction temperatures can be the result of high current
operation, poor circuit board design, and/or high ambient tem-
perature. A 20癈 hysteresis is included; thus, when thermal
shutdown occurs, the ADP2140 does not return to operation
until the on-chip temperature drops below 130癈. When
emerging from a thermal shutdown, soft start initiates.
SOFT START
The ADP2140 has an internal soft start function that ramps the
output voltage in a controlled manner upon startup, thereby
limiting the inrush current. This prevents possible input voltage
drops when a battery or a high impedance power source is con-
nected to the input of the converter.
CURRENT LIMIT
The ADP2140 has protection circuitry to limit the direction and
amount of current to 1000 mA flowing through the power switch
and synchronous rectifier. The positive current limit on the power
switch limits the amount of current that can flow from the input
to the output, and the negative current limit on the synchronous
rectifier prevents the inductor current from reversing direction
and flowing out of the load.
The ADP2140 also provides a negative current limit to prevent
an excessive reverse inductor current when the switching section
sinks current from the load in forced continuous conduction
mode. Under negative current limit conditions, both the high-
side and low-side switches are disabled.
POWER-GOOD PIN
The ADP2140 has a dedicated pin (PG) to signal the state of the
monitored output voltages. The voltage monitor circuit has an
active high, open-drain output requiring an external pull-up
resistor typically supplied from the I/O supply rail, as shown
in . The voltage monitor circuit has a small amount
of hysteresis and is deglitched to ensure that noise or external
perturbations do not trigger the PG line.
LDO SECTION
The ADP2140 low dropout linear regulator uses an advanced
proprietary architecture to achieve low quiescent current, and
high efficiency regulation. It also provides high power supply
rejection ratio (PSRR), low output noise, and excellent line and
load transient response with just a small 1 糉 ceramic output capa-
citor. The wide input voltage range of 1.65 V to 5.5 V allows it to
operate from either the input or output of the buck. Supply current
in shutdown mode is typically 0.3 礎.
Internally, the LDO consists of a reference, an error amplifier, a
feedback voltage divider, and a pass device. The output current
is delivered via the pass device, which is controlled by the error
amplifier, forming a negative feedback system ideally driving
the feedback voltage to be equal to the reference voltage. If the
feedback voltage is lower than the reference voltage, the negative
feedback drives more current, increasing the output voltage. If
the feedback voltage is higher than the reference voltage, the
negative feedback drives less current, decreasing the output
voltage. The positive supply for all circuitry, except the pass
device, is the VIN1 pin.
The LDO has an internal soft start that limits the output voltage
ramp period to approximately 130 祍.
The LDO is available in 0.8 V , 1.0 V , 1.1 V , 1.2 V , 1.3 V , 1.5 V , 2.5 V ,
2.8 V, 3.0 V, and 3.3 V output voltage options.
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