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參數資料
| 型號： | ADP3050 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 200 kHz, 1 A High-Voltage Step-Down Switching Regulator |
| 中文描述： | 200千赫，1高電壓降壓型開關穩壓器 |
| 文件頁數： | 13/16頁 |
| 文件大小： | 191K |
| 代理商： | ADP3050 |
ADP3050
–
13
–
REV. 0
to determine the total output variation. Use 1% resistors placed
close to the FB pin to prevent noise pick up.
FREQUENCY COMPENSATION
The ADP3050 uses a unique compensation scheme that allows the
use of any type of output capacitor. The designer is not limited to a
specific type of capacitor nor a specific ESR range. External compen-
sation allows the designer to optimize the loop for transient response
and system performance. The values for R
C
and C
C
will set the
pole and zero locations for the error amplifier to compensate the
regulator loop.
For tantalum output capacitors, the typical compensation values
are R
C
= 4 k
and C
C
= 1 nF; for ceramics, the typical values
are R
C
= 4 k
and C
C
= 4.7 nF. These values may not be opti-
mized for all designs, but they should provide a good starting
point for selecting the final compensation values. Other types of
output capacitors will require different values of C
C
between
0.5 nF and 10 nF. Typically, the lower the ESR of the output
capacitor, the larger the value for C
C
. Normal variations in
capacitor ESR, output capacitance, and inductor value (due
to production tolerances, changes in operating point, changes
in temperature) will affect the loop gain and phase response.
Always check the final design over its complete operating range
to ensure proper regulator operation.
Adjusting the R
C
and C
C
values can optimize the compensation for
your system. Use the typical values above as a starting point, then
try increasing and decreasing each independently and observing the
transient response. An easy way to check the transient response of
the design is by observing the output while pulsing the load current
at a rate of around 100 Hz to 1 kHz. There should be some slight
ringing at the output when the load pulses, but this should not be
excessive (just a few rings). The frequency of this ringing shows
the approximate unity gain frequency of the loop. Again, always
check the design over its full operating range of input voltage,
output current, and temperature to ensure that the loop is compen-
sated correctly.
In addition to setting the zero location, R
C
also sets the high
frequency gain of the error amplifier. If this gain is too large,
output ripple voltage will appear at the COMP pin (the output
of the error amplifier) with enough amplitude to interfere with
normal regulator operation. If this happens, subharmonic
switching will occur (the pulsewidth of the switch waveform will
change, even though the output voltage stays regulated). The
voltage ripple at the COMP pin should be kept below about 100
mV to prevent this from occurring. The amount of ripple can be
estimated by the following formula, where g
m
is the error ampli-
fier transconductance (g
m
= 1,250
μ
Mho):
(
V
g
R
I
ESR
V
V
COMP, RIPPLE
m
C
RIPPLE
FB
OUT
=
×
)
×
×
(
)
×
(8)
For example: a 12 V to 5 V, 800 mA regulator with an inductor
of L = 47
μ
H has
I
RIPPLE
= 310 mA (example from earlier section);
if a 100
μ
F tantalum output capacitor with a maximum ESR of
100 m
and compensation values of R
C
= 4 k
and C
C
= 1 nF
are used. The ripple voltage at the COMP pin will be:
(
1 20
5 0
V
.
.
COMP, RIPPLE
=
×
×
×
)
×
×
(
)
×
=
1 250
,
10
4
10
0 310
.
0 1
.
37 2
6
3
.
mV
If this ripple voltage were more than 100 mV, R
C
would need to
be decreased to prevent subharmonic switching. Typical values
for R
C
will be in the range of 2 k
to 10 k
.
For output voltages greater than 5 V, it may be necessary to add a
small capacitor in parallel with R2, as shown in Figure 23. This
will improve stability and transient response. For tantalum output
capacitors, the typical value for C
F
is 100 pF. For ceramic output
capacitors, the typical value for C
F
is 400 pF.
CURRENT LIMIT/FREQUENCY FOLDBACK
The ADP3050 uses a cycle-by-cycle current limit to protect the
device under fault and high stress conditions. When the current
limit is exceeded, the power switch turns off until the beginning
of the next oscillator cycle. If the voltage on the feedback pin
drops below 80% of its nominal value, the oscillator frequency
starts to decrease (see Figure 15 in the Typical Performance
Characteristics section). The frequency gradually reduces to a
minimum value of around 80 kHz (this minimum occurs when
the feedback voltage falls to 30% of its nominal value). This
reduces the power dissipation in the IC, the external diode, and
the inductor during short circuit conditions. This frequency
foldback method provides complete device fault protection with-
out interfering with the normal device operation.
BIAS PIN CONNECTION
To help improve efficiency, most of the internal operating current
can be drawn from the lower voltage regulated output voltage
instead of from the input supply. For example, if the input voltage
is 24 V and the output voltage is 5 V, a quiescent current of 4 mA
will waste 96 mW if drawn from the input supply, but only 20 mW
is drawn from the regulated 5 V output. This power savings will be
most evident at high input voltages and low load currents. The out-
put voltage must be 3 V or higher to take advantage of this feature.
BOOSTED DRIVE STAGE
An external capacitor and diode are used to provide the boosted
voltage needed for the special drive stage. If the output voltage is
above 4 V, connect the anode of the boost diode to the regulated
output; for output voltages less than or equal to 3 V, connect it to
the input supply. For some low voltage systems (i.e., 5 V to 3.3 V
converters), the anode of the boost diode can be connected to
either the input or output voltage. During switch off-time, the
boost capacitor is charged up to the voltage at the anode of the
boost diode. When the switch turns on, this voltage is added to
the switch voltage (the boost diode is reverse-biased) providing a
voltage higher than the input supply. The peak voltage appearing
on the BOOST pin will be the sum of the input voltage and the
boost voltage (either V
IN
+ V
OUT
or 2 V
IN
). Ensure that this peak
voltage does not exceed the BOOST pin maximum rating of 45 V.
For most applications, a 1N4148 or 1N914 type diode can be
used with a 220 nF capacitor. A 470 nF capacitor may be needed
for output voltages between 3 V and 4 V. The boost capacitor
should have an ESR less than 2
to ensure that it will be adequately
charged up during switch off-time. Most any type of film or ceramic
capacitor can be used.
START-UP/MINIMUM INPUT VOLTAGE
For most designs, the regulated output voltage provides the
boosted voltage for the drive stage. During startup, the output
voltage is zero, so there is no boosted supply for the drive stage.
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PDF描述 |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADP3050AR | 制造商:Analog Devices 功能描述:Conv DC-DC Single Step Down 3.6V to 30V 8-Pin SOIC N 制造商:Rochester Electronics LLC 功能描述:HIGH VOLTAGE STEP DOWN SWITCHING REG. - Bulk 制造商:Analog Devices 功能描述:IC SWITCHING REGULATOR |
| ADP3050AR3.3 | 制造商:Analog Devices 功能描述:IC ((NS)) |
| ADP3050AR-3.3 | 功能描述:IC REG BUCK 3.3V 1A 8SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩壓器 - DC DC 開關穩壓器 系列:- 設計資源:Design Support Tool 標準包裝:1 系列:- 類型:升壓（升壓） 輸出類型:固定 輸出數:1 輸出電壓:3V 輸入電壓:0.75 V ~ 2 V PWM 型:- 頻率 - 開關:- 電流 - 輸出:100mA 同步整流器:是 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-5 細型，TSOT-23-5 包裝:剪切帶 (CT) 供應商設備封裝:TSOT-23-5 其它名稱:AS1323-BTTT-30CT |
| ADP3050AR-3.3-REEL | 制造商:Analog Devices 功能描述:Conv DC-DC Single Step Down 3.6V to 30V 8-Pin SOIC N T/R |
| ADP3050AR-3.3-RL7 | 功能描述:IC REG BUCK 3.3V 1A 8SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩壓器 - DC DC 開關穩壓器 系列:- 標準包裝:2,500 系列:- 類型:升壓（升壓） 輸出類型:可調式 輸出數:1 輸出電壓:1.24 V ~ 30 V 輸入電壓:1.5 V ~ 12 V PWM 型:電流模式，混合 頻率 - 開關:600kHz 電流 - 輸出:500mA 同步整流器:無 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) 供應商設備封裝:8-SOIC |
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