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參數資料
型號: ADP3050AR-5
廠商: ANALOG DEVICES INC
元件分類: 穩壓器
英文描述: Circular Connector Cable Assembly; Connector Type A:Circular Receptacle; Connector Type B:Stripped End Leads; Cable Length:10ft RoHS Compliant: Yes
中文描述: 2.1 A SWITCHING REGULATOR, 240 kHz SWITCHING FREQ-MAX, PDSO8
封裝: MS-012AA, SOIC-8
文件頁數: 14/16頁
文件大小: 191K
代理商: ADP3050AR-5
ADP3050
14
REV. 0
To deal with this problem, the ADP3050 contains a backup
drive stage to get everything started. As the output voltage
increases, so will the boost voltage. When the boost voltage
reaches around 2.5 V, the switch drive will transition smoothly
from the backup driver to the boosted driver. If the boost
voltage should decrease below around 2.5 V (i.e., short circuit,
overload condition), the backup stage will again take over to
provide switch drive. The minimum input voltage needed for
the ADP3050 to function correctly is about 3.6 V (this will
ensure proper operation of the internal circuitry), but a small
amount of headroom is needed for all step-down regulators.
The following formula gives the approximate minimum input
voltage needed for a given system, where V
SAT
is the switch
saturation voltage (see Figure 13 for the appropriate value of
V
SAT
). Figure 11 also shows the typical minimum input voltage
needed for 3.3 V and 5 V systems.
V
V
V
IN
OUT
SAT
(MIN)
.
=
+
0 85
(9)
THERMAL CONSIDERATIONS
Several factors contribute to IC power dissipation: ac and dc
switch losses, boost current, and quiescent current. The following
formulas can be used to calculate these losses to determine the
power dissipation of the IC. These formulas assume continuous
mode operation, but they provide a reasonable estimate for discon-
tinuous mode systems (do not use these formulas to calculate
efficiency at light loads).
Switch loss:
Boost current loss:
P
I
V
V
V
t
I
V
f
SW
OUT
SAT
OUT
IN
OV
OUT
IN
SW
=
×
×
+
×
×
×
(
)
(10)
P
I
β
V
V
BOOST
OUT
SW
OUT
2
IN
=
×
(11)
Quiescent current loss:
P
where
V
SAT
is ~0.6 V at I
OUT
= 800 mA (taken from Figure 13),
f
SW
is the switch frequency (200 kHz),
t
OV
is the switch current/voltage
overlap time (~50 ns),
β
SW
is the current gain of the NPN power
switch (~50),
I
Q
is the quiescent current drawn from
V
IN
(~1 mA)
and
I
BIAS
is the quiescent current drawn from
V
OUT
(~4 mA).
V
(
I
V
(
I
Q
IN
Q
OUT
BIAS
=
×
)
+
×
)
(12)
For example: for a 5 V to 3.3 V system with I
OUT
= 800 mA:
P
(
mW
SW
=
×
×
+
×
×
×
×
×
)
=
0.
0 6
.
3.
5 0
.
50
10
0 8
.
5 0
.
200
10
357
9
3
P
mW
BOOST
=
(
×
=
0.
50
3 3
5 0
.
(
35
2
.
P
For a total IC power dissipation of:
mW
Q
=
)
+
×
×
)
=
5 10
3 3
.
4
10
18
3
3
P
P
410
P
P
mW
TOTAL
SW
BOOST
Q
=
=
+
+
(13)
The ADP3050 uses a thermally enhanced SO-8 package with a
package thermal resistance,
θ
JA
, of around 80
°
C/W for a four-
layer board (poor layout techniques will result in a higher thermal
resistance). This allows the ADP3050 to provide 1 A load currents
in an SO-8 package. The maximum die temperature, T
J
, can be
calculated using the thermal resistance and the maximum ambient
temperature:
=
+
θ
T
For the previous example (5 V to 3.3 V at 800 mA system, SO-8
thermally enhanced package using good layout techniques) with
a worst-case ambient temperature of 70
°
C:
°
+
°
70
80
C
C W
The maximum operating junction (die) temperature is 125
°
C, so
this system will operate within the safe limits of the ADP3050.
Check the die temperature at minimum and maximum supply
voltages to ensure proper operation under all conditions. The PC
board and its copper traces will provide sufficient heat-sinking,
but be sure to follow the layout suggestions in the Board Layout
Guidelines section. For any design that combines high output
current with high duty cycle and/or high input voltage, the junc-
tion temperature must be calculated to ensure normal operation.
Always use the equations in this section to estimate the power
dissipation.
T
P
A
A
TOTAL
J
J
×
(14)
T
/
J
=
×
=
°
0.
103
C
BOARD LAYOUT GUIDELINES
A good board layout is essential when designing a switching
regulator. The high switching currents along with parasitic
wiring inductances can generate significant voltage transients and
cause havoc in sensitive circuits. For best results, keep the main
switching path as tight as possible (keep L1, D1, C
IN
, and C
OUT
close together) and minimize the copper area of the SWITCH and
BOOST nodes (without violating current density requirements) to
reduce the amount of noise coupling into other sensitive nodes.
IN
ADP3050
SWITCH
GND
V
IN
GND
+
C
IN
+
C
OUT
D1
L1
V
OUT
GND
Figure 24. Main Switching Path
The external components should be located as close to the
ADP3050 as possible. For best thermal performance, use wide
copper traces for all IC connections, and always connect the
GND pin to a large piece of copper or ground plane. The ad-
ditional copper will improve heat transfer from the IC, greatly
reducing the package thermal resistance. Further improve-
ments of the thermal performance can be made by using
multilayer boards and using vias to transfer heat to the other
layers. A single layer board layout is shown in Figure 25. The
amount of copper used for the input, output, and ground
traces can be reduced, but were made large to improve the
thermal performance. For the 5 V and 3.3 V versions, leave
out R1 and R2; for the Adjustable version, remove the trace
that shorts out R2. Route all sensitive traces and components,
such as those associated with the feedback and compensation away
from the BOOST and SWITCH traces.
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