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參數資料
| 型號： | ADP3160 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 5-Bit Programmable 2-Phase Synchronous Buck Controller |
| 中文描述： | 5位可編程2相同步降壓控制器 |
| 文件頁數： | 11/16頁 |
| 文件大小： | 292K |
| 代理商： | ADP3160 |
REV. B
ADP3160/ADP3167
–11–
The optimal implementation of voltage positioning, ADOPT,
will create an output impedance of the power converter that is
entirely resistive over the widest possible frequency range, includ-
ing dc, and equal to the maximum acceptable ESR of the output
capacitor array. With the resistive output impedance, the output
voltage will droop in proportion with the load current at any
load current slew rate; this ensures the optimal positioning and
allows the minimization of the output capacitor.
With an ideal current-mode controlled converter, where the
average inductor current would respond without delay to the
command signal, the resistive output impedance could be
achieved by having a single-pole roll-off of the voltage gain of
the voltage-error amplifier. The pole frequency must coincide
with the ESR zero of the output capacitor. The devices use constant
frequency current-mode control, which is known to have a
nonideal, frequency dependent command signal to inductor current
transfer function. The frequency dependence manifests in the
form of a pair of complex conjugate poles at one-half of the switch-
ing frequency. A purely resistive output impedance could be
achieved by canceling the complex conjugate poles with zeros at
the same complex frequencies and adding a third pole equal to
the ESR zero of the output capacitor. Such a compensating network
would be quite complicated. Fortunately, in practice it is
sufficient to cancel the pair of complex conjugate poles with a
single real zero placed at one-half of the switching frequency.
Although the end result is not a perfectly resistive output imped-
ance, the remaining frequency dependence causes only a small
percentage of deviation from the ideal resistive response. The
single-pole and single-zero compensation can be easily implemented
by terminating the g
m
error amplifier with the parallel combina-
tion of a resistor and a series RC network.
The first step in the design of the feedback loop compensa-
tion is to determine the targeted output resistance, R
E(MAX)
, of the
power converter using Equation 4. The compensation can then
be tailored to create that output impedance for the power
converter, and the quantity of output capacitors can be chosen
to create a net ESR that is less than or equal to R
E(MAX)
.
The next step is to determine the total termination resistance of
the g
m
amplifier that will yield the correct output resistance:
￥
￥
=
￥
.
.
2 2
1 5
where n
I
is the division ratio from the output voltage signal of
the g
m
amplifier to the PWM comparator (CMP1), g
m
is the
transconductance of the g
m
amplifier itself, and the factor of 2 is
the result of the 2-phase configuration. Note that the internal
current multiplier (n
I
) is 12.5 for the ADP3160, but is 25 for
the ADP3167. For this example, assume that we use the
Rubycon capacitors at the output with their ESR of 1.44 m
W
.
Once R
T
is known, the two resistors that make up the divider
from the REF pin to output of the g
m
amplifier (COMP pin)
must be calculated. The resistive divider introduces an offset to
the output of the g
m
amplifier that, when reflected back through
the gain of the g
m
stage, accurately positions the output voltage
near its allowed maximum at light load. Furthermore, the output
of the g
m
amplifier sets the current sense threshold voltage. At no
load, the current sense threshold is increased by the peak of the
ripple current in the inductor and reduced by the delay between
R
n
R
g
R
12 5
R
m
mmho
m
k
T
I
SENSE
m
E MAX
(
.
T
=
￥
￥
W
W ￥
=
W
)
.
2
4
2
7 57
(22)
the data sheet for the FDB7030L, the value of Q
G
is about 35 nC
and the peak gate drive current provided by the ADP3412 is
about 1 A. In the third term, Q
RR
is the charge stored in the
body diode of the low-side MOSFET at the valley of the inductor
current. The data sheet of the FDB8030L does not give that
information, so an estimated value of 150 nC is used. The esti-
mate is based on information found on the data sheet of a
similar device, the IRF7809. In both terms, f
SW
is the actual
switching frequency of the MOSFETs, or 200 kHz. I
L(PK)
is the
peak current in the inductor, or 32.8 A.
Substituting the above data in Equation 19, and using the worst-
case value for the MOSFET resistance yields a conduction loss
of 0.96 W, a turn-off loss of 2.75 W, and a turn-on loss of 0.72 W.
Thus the worst-case total loss in a high-side MOSFET is 4.43 W.
The worst-case low-side MOSFET dissipation is:
P
R
I
P
m
A
W
LSF
DS ON LS
W ￥
.
5 6
LSF MAX
=
)
LSF
=
=
￥
25
(
)
(
)
(
.
2
2
3 5
(19)
(Note that there are no switching losses in the low-side MOSFET.)
C
IN
Selection and Input Current di/dt Reduction
In continuous inductor-current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to V
OUT
/V
IN
and an amplitude of one-half of the
maximum output current. To prevent large voltage transients, a
low ESR input capacitor sized for the maximum rms current
must be used. The maximum rms capacitor current is given by:
I
I
D
D
I
A
A
C RMS
(
O
2
53 4
HSF
HSF
C RMS
(
)
)
(
)
.
2
.
–(
.
)
.
=
￥
-
￥
=
￥
￥
=
2
2
2
0 133
2
0 133
11 9
2
2
(20)
Note that the capacitor manufacturer’s ripple current ratings are
often based on only 2000 hours of life. This makes it advisable
to further derate the capacitor, or to choose a capacitor rated at
a higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
four 270
m
F, 16 V OS-CON capacitors.
The ripple voltage across the three paralleled capacitors is:
To reduce the input current di/dt to below the recommended
maximum of 0.1 A/
m
s, an additional small inductor (L > 1
m
H @
15 A) should be inserted between the converter and the supply
bus. That inductor also acts as a filter between the converter and
the primary power source.
Feedback Loop Compensation Design for ADOPT
Optimized compensation of the ADP3160 and ADP3167 allow
the best possible containment of the peak-to-peak output voltage
deviation. Any practical switching power converter is inherently
limited by the inductor in its output current slew rate to a value
much less than the slew rate of the load. Therefore, any sudden
change of load current will initially flow through the output capaci-
tors, and assuming that the capacitance of the output capacitor
is larger than the critical value defined by Equation 5, this will
produce a peak output voltage deviation equal to the ESR of the
output capacitor times the load current change.
V
I
n
53 4
ESR
n
A
￥
D
C
n
W+
f
V
m
4
F
kHz
mV
C RIPPLE
(
O
C
C
ê
HSF
C
IN
SW
0 133
270
C RIPPLE
(
)
)
.
2
.
=
￥
+
￥
￥
ê
ˉ
=
￥
m
￥
18
4
200
137
(21)
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相關代理商/技術參數 |
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|---|---|
| ADP3160JR | 制造商:Rochester Electronics LLC 功能描述:5BIT PRGRM'BLE 2PHASE SYNCRO BUCK CNTRLR - Bulk |
| ADP3160JR-REEL | 制造商:Rochester Electronics LLC 功能描述:5BIT PRGRM'BLE 2PHASE SYNCRO BUCK CNTRLR - Tape and Reel |
| ADP3160JR-REEL7 | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| ADP3161 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Bit Programmable 2-Phase Synchronous Buck Controller |
| ADP3161JR | 制造商:Rochester Electronics LLC 功能描述:5-BIT PROG. 2-PHASE SYNC. BUCK CNTRLR. - Bulk |
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