
REV. B
ADP3160/ADP3167
–13–
2200 F 10
RUBYCON 6.3V MBZ SERIES
13m ESR (EACH)
Q3
FDB7030L
V
CC(CORE)
1.1V – 1.85V
45A
Q1
FDB7030L
Q2
FDB7035L
C15
C14
C13
C12
12V V
CC
12V V
CC
RTN
R2
20.6k
C
1.8nF
R4
4m
R3
16.5k
Q4
FDB7035L
1
2
3
4
8
7
6
5
BST
IN
DLY
VCC
DRVH
SW
PGND
DRVL
U2
ADP3412
U1
ADP3167
C11 C16 C17 C18 C19
C28
V
CC(CORE)
RTN
D1
MBR052LTI
Q5
2N3904
L2
600nH
L1
600nH
C10
1 F
D2
MBR052LTI
C7
15pF
C5
1 F
Z1
ZMM5236BCT
R5
2.4k
C22 1nF
C4
4.7 F
R6
10
C21
15nF
V
IN
5V
V
IN
RTN
C26
4.7 F
C8
15pF
C6
1 F
C9
1 F
R7
20
C2
100pF
C1
150pF
R1
1k
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VID4
VID3
VID2
VID1
VID0
COMP
FB
CT
VCC
REF
CS–
PWM1
PWM2
CS+
PWRGD
GND
1
2
3
4
8
7
6
5
BST
IN
DLY
VCC
DRVH
SW
PGND
DRVL
U3
ADP3412
1800 F 4
RUBYCON MBZ SERIES
C20 C24
FROM
CPU
C25 C27
Figure 8. 45 A Athlon Duron CPU Supply Circuit
AMD Athlon Design Example
The design parameters for a typical high-performance AMD
CPU application (see Figure 8) are as follows:
Input Voltage (V
IN
) = 5 V
Nominal Output Voltage (V
OUT
) = 1.7 V
Static Output Tolerance (V ) = (V+) – (V–) =
50 mV – (–50 mV) = 100 mV
Maximum Output Current (I
O
) = 45 A
Output Current di/dt < 50 A/ s
Using the design procedure previously shown, the final values
for this application were calculated, and are shown in Figure 8.
Average Output Voltage (V
(V+) + (V–)
OUT
+
) =
V
2
= 1.7 V
AVG
LAYOUT AND COMPONENT PLACEMENT GUIDELINES
The following guidelines are recommended for optimal perfor-
mance of a switching regulator in a PC system.
General Recommendations
1. For good results, at least a four-layer PCB is recommended.
This should allow the needed versatility for control circuitry
interconnections with optimal placement, a signal ground
plane, power planes for both power ground and the input
power (e.g., 5 V), and wide interconnection traces in the
rest of the power delivery current paths. Keep in mind that
each square unit of 1 ounce copper trace has a resistance of
~0.53 m
W
at room temperature.
2. Whenever high currents must be routed between PCB layers,
vias should be used liberally to create several parallel current
paths so that the resistance and inductance introduced by
these current paths is minimized and the via current rating is
not exceeded.
3. If critical signal lines (including the voltage and current
sense lines of the ADP3160) must cross through power
circuitry, it is best if a signal ground plane can be interposed
between those signal lines and the traces of the power
circuitry. This serves as a shield to minimize noise injec-
tion into the signals at the expense of making signal ground
a bit noisier.
4. The power ground plane should not extend under signal
components, including the ADP3160 itself. If necessary,
follow the preceding guideline to use the signal ground
plane as a shield between the power ground plane and the
signal circuitry.
5. The GND pin of the ADP3160 should be connected first to
the timing capacitor (on the CT pin), and then into the
signal ground plane. In cases where no signal ground plane
can be used, short interconnections to other signal ground
circuitry in the power converter should be used.
1
Ch1
500mV
20mV
700mV
Ch1
M 200 s
Ch2
2
Figure 7. Transient Response of the 53.4 A
Design Example of Figure 6