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參數資料
| 型號： | ADP3166JRU-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 5-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller |
| 中文描述： | SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | TSSOP-28 |
| 文件頁數： | 9/20頁 |
| 文件大小： | 351K |
| 代理商： | ADP3166JRU-REEL7 |
REV. 0
ADP3166
–9–
Dynamic VID
The ADP3166 incorporates the ability to dynamically change
the VID input while the controller is running. This allows the
output voltage to change while the supply is running and sup-
plying current to the load. This is commonly referred to as
VID on-the-fly (OTF). A VID-OTF can occur under either
light load or heavy load conditions. The processor signals the
controller by changing the VID inputs in multiple steps from
the start code to the finish code. This change can be either
positive or negative.
When a VID input changes state, the ADP3166 detects the
change and blanks the DAC for a minimum of 400 ns. This
time is to prevent a false code due to logic skew while the six
VID inputs are changing. Additionally, the first VID change
initiates the PWRGD blanking function for a minimum of
100
μ
s to prevent a false PWRGD event. Each VID change will
reset the internal timer.
Power Good Monitoring
The power good comparator monitors the output voltage via the
CSREF pin. The PWRGD pin is an open-drain output whose
high level (when connected to a pull-up resistor) indicates that
the output voltage is within the nominal limits specified previ-
ously, based on the VID voltage setting. PWRGD will go low if
the output voltage is outside of this specified range. PWRGD is
blanked during a VID-OTF event for a period of 100
μ
s to
prevent false signals during the time the output is changing.
Output Crowbar
As part of the protection for the load and output components of
the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) and the CROWBAR logic output goes
high when the output voltage exceeds the upper power good
threshold. This crowbar action releases once the output volt-
age has fallen back within specifications if no other faults are
present. The release threshold is approximately 400 mV.
Turning on the low-side MOSFETs pulls down the output as
the reverse current builds up in the inductors. If the output
overvoltage is due to a short of the high-side MOSFET, this
action current limits the input supply or blow its fuse, protect-
ing the microprocessor from destruction.
The CROWBAR output can be used to signal an external input
crowbar or other protection circuit.
Output Enable and UVLO
The input VCC must be higher than the UVLO threshold and the
EN pin must be higher than its logic threshold for the ADP3166 to
begin switching. IF UVLO is less than the threshold or the EN pin
is a logic low, the ADP3166 is disabled. This holds the PWM
outputs at ground, shorts the DELAY capacitor to ground, and
holds the ILIMIT pin at ground.
In the application circuit, the ILIMIT pin should be connected
to the
OD
pins of the ADP3418 drivers. Because ILIMIT is
grounded, this disables the drivers such that both DRVH and
DRVL are grounded. This feature is important to prevent dis-
charging of the output capacitors when the controller is shut off.
If the driver outputs were not disabled, a negative voltage could
be generated on the output due to the high current discharge of
the output capacitors through the inductors.
APPLICATION INFORMATION
The design parameters for a typical AMD K8 compliant CPU
application are as follows:
Input voltage (V
IN
) = 12 V
VID setting voltage (V
VID
) = 1.500 V
Duty cycle (D) = 0.125
Maximum static output voltage error (
±
V
SERR
) =
±
50 mV
Maximum dynamic output voltage error (
±
V
DERR
) =
±
70 mV
Error voltage allowed for controller and ripple (
±
V
RERR
) =
±
20 mV
Maximum output current (I
O
) = 56 A
Maximum output current step ( I
O
) = 24 A
Static output droop resistance (R
O
) based on:
a) No load output voltage set at upper output
voltage limit.
V
ONL
= V
VID
+ V
SERR
– V
RERR
= 1.530 V
b) Full load output voltage set at lower output
voltage limit.
V
OFL
= V
VID
– V
SERR
+ V
RERR
= 1.470 V
R
O
= (V
ONL
– V
OFL
)/ (I
O
) = (1.530 V – 1.470 V)/(56A) =
1.1 m
Dynamic output droop resistance (R
OD
) based on:
a) Output current step to no load with output voltage
set at upper output dynamic voltage limit.
V
ONLD
= V
VID
+ V
DERR
– V
RERR
= 1.550 V
b) Output voltage prior to load change
(at I
OUT
= I
O
).
V
OL
= V
ONL
– ( I
O
R
O
)= 1.504 V
R
OD
= (V
ONLD
– V
OL
)/ ( I
O
) = (1.550 V – 1.504 V)/(24A) =
1.9 m
Number of phases (n) = 3
Switching frequency per phase (f
SW
) = 330 kHz
Setting the Clock Frequency
The ADP3166 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (R
T
). The clock
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and input and output capacitors.
With n = 3 for three phases, a clock frequency of 990 kHz sets
the switching frequency of each phase, f
SW
, to 330 kHz, which
represents a practical trade-off between the switching losses and
the sizes of the output filter components. Figure 1 shows that to
achieve a 990 kHz oscillator frequency, the correct value for R
T
is 200 k
. Alternatively, the value for R
T
can be calculated using
1
(
pF
–
R =
n
f
.
1 5
SW
5 83
1
M
×
×
)
(1)
where 5.83 pF and 1.5 M
are internal IC component values.
For good initial accuracy and frequency stability, it is recom-
mended to use a 1% resistor.
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