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參數資料
| 型號： | ADP3203JRU-10-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 2-Phase IMVP-II & IMVP-III Core Controller for Mobile CPUs |
| 中文描述： | 2相IMVP的-Ⅱ |
| 文件頁數： | 5/12頁 |
| 文件大?。?/td> | 153K |
| 代理商： | ADP3203JRU-10-RL |
ADP3203
REV. PrD
–5–
PRELIMINARY TECHNICAL DATction Description
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Function
1
HYSSET
Hysteresis Set. This is an analog I/O pin whose output is a fixed voltage reference and whose input
is a current that is programmed by an external resistance to ground. The current is used in the IC
to set the hysteretic currents for the Core Comparator and the Current Limit Comparator.
Modification of the resistance will affect both the hysteresis of the feedback regulation and the
current limit set point and hysteresis.
2
DSHIFT
Deep Sleep Shift. This is an analog I/O pin whose output is the VID reference voltage and whose
input is a current that is programmed by an external resistance to ground. The current is used in
the IC to set a switched bias current out of the RAMP pin, depending on whether it is activated by
the DSLP# signal. When activated, this added bias current creates a downward shift of the
regulated core voltage to a predetermined optimum level for regulation corresponding to Deep
Sleep mode of CPU operation. The use of the VID code as the reference makes the Deep Sleep
offset a fixed percentage of the VID setting, as required by specifications.
3
BSHIFT
Battery Optimized Mode (
BOM
) Shift. This is an analog I/O pin whose output that is the VID
reference voltage and whose input current is programmed by an external resistance to ground. The
current is used in the IC to set a switched bias current out of the RAMP pin, depending on
whether it is activated by the
BOM
signal. When activated, this added bias current creates a
downward shift of the regulated core voltage to a predetermined optimum level for regulation
corresponding to Battery Optimized Mode of CPU operation. The use of the VID code as the
reference makes the DSHIFT a fixed percentage of the VID setting, as required by specifications.
4–8
VID[4:0]
Voltage Identification Inputs. These are the VID inputs for logic control of the programmed
reference voltage that appears at the DACOUT pin, and, via external component configuration, is
used for setting the output voltage regulation point. The VID pins have a specified internal pullup
current such that, if left open, the pins will default to a logic high state. The VID code does not set
the DAC output voltage directly but through a transparent latch which is clocked by the
BOM
pin's GMUXSEL signal rising and falling edge.
9
BOM
Battery Optimized Mode Control (active low). This is a digital input pin that corresponds to the
system's GMUXSEL signal that corresponds to Battery Optimized Mode of the CPU operation in
its active low state and Performance Optimized Mode (POM) in its deactivated high state. The
signal also controls the optimal positioning of the core voltage regulation level by offsetting it
downwards in Battery Optimized Mode according to the functionality of the BSHIFT and RAMP
pins. It is also used to initiate a masking period for the PWRGD signal whenever a GMUXSEL
signal transition occurs.
10
DSLP
Deep Sleep Mode Control (active low). This is a digital input pin corresponding to the system's
STP CPU
signal which, in its active state, corresponds to Deep Sleep mode of the CPU operation,
which is a subset operating mode of either BOM or POM operation. The signal controls the
optimal positioning of the core voltage regulation level by offsetting it downwards according to the
functionality of the DSHIFT and RAMP pins.
11
DPRSLP
Deeper Sleep Mode Control (active high). This is a digital input pin corresponding to the system's
DPRSLPVR signal corresponding to Deeper Sleep mode of the CPU operation. The signal when
it is activated controls the DAC output voltage by disconnecting the VID signals from the DAC
input and setting a specified internal Deeper Sleep code instead. At de-assertion of the
DPRSLPVR signal, the DAC output voltage returns to the voltage level determined by the
external VID code. The DPRSLPVR signal is also used to initiate a blanking period for the
PWRGD signal to disable its response to a pending dynamic core voltage change corresponds to
the VID code transition.
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| ADP3203JRU-10-RL7 | 2-Phase IMVP-II & IMVP-III Core Controller for Mobile CPUs |
| ADP3203 | 2-Phase IMVP-II & IMVP-III Core Controller for Mobile CPUs |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADP3203JRU-10-RL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Phase IMVP-II & IMVP-III Core Controller for Mobile CPUs |
| ADP3204 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUs |
| ADP3204JCP | 制造商:AD 制造商全稱:Analog Devices 功能描述:3-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUs |
| ADP3204JCP-REEL | 制造商:Analog Devices 功能描述: |
| ADP3204JCP-REEL7 | 制造商:Rochester Electronics LLC 功能描述:3 PHASE PEAK/PEAK DC/DC MODE CONTROLLER - Tape and Reel |
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