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參數資料
| 型號： | ADP3421 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | Geyserville-Enabled DC-DC Converter Controller for Mobile CPUs |
| 中文描述： | 蓋瑟維爾啟用的DC - DC轉換器控制器的移動處理器 |
| 文件頁數： | 5/12頁 |
| 文件大?。?/td> | 146K |
| 代理商： | ADP3421 |
REV. A
ADP3421
–5–
Pin
Mnemonic
Function
15
16
SD
PWRGD
Shutdown Input. When this pin is pulled low, the IC shuts down and all regulation functions will be disabled.
Power Good Output. This signal will go high only when the
SD
pin is high to allow IC operation, the UVLO
and VCC pins are above their respective start-up thresholds, the SSC and SSL pins are above a voltage where
soft start is completed, and the voltage at the CORE pin is within the specified limits of the programmed VID
voltage. By choosing the soft-start capacitor for the core larger than that for the linear regulators, at start-up
the core and linear outputs should all be in regulation before PWRGD is asserted.
Undervoltage Lockout Input. This pin monitors the input voltage through a resistor divider. When the pin
voltage is below a specified threshold, the IC enters into UVLO mode regardless of the status of
SD
. When
in UVLO mode, a current source is switched on at this pin, which sinks current from the external resistor
divider. The generated UVLO hysteresis is equal to the current sink value times the upper divider resistor.
Linear Regulator Soft Start. During power-up, an external soft-start capacitor is charged by a current source
to control the ramp-up rates of the linear regulators.
Core Voltage Soft Start. During power-up, an external soft-start capacitor is charged by a current source to
control the ramp-up rate of the core voltage.
Core Converter Voltage Monitor. This pin is used to monitor the core voltage for power good verification.
VID-Programmed Digital-to-Analog Converter Output. This voltage is the reference voltage for output
voltage regulation.
Ground
Logic-Level Drive Signal Output of Core Controller. This pin provides the drive command signal to the IN
pin of the ADP3410 driver. This pin is not capable of directly driving a power MOSFET.
Power Supply
Current Ramp Input. This pin provides the negative feedback for the core output voltage. The switched sink/
source current from this pin, which is set up at the VHYS pin, works against the terminating resistance at this
pin to set the hysteresis for the hysteretic control.
Regulation Voltage Summing Input. In the recommended configuration, the DACOUT voltage and the core
voltage are summed at this pin to establish regulation with output voltage positioning.
Current Limit Positive Sense. This pin senses the positive node of the current sense resistor.
Current Limit Negative Sense. This pin connects through a resistor to the negative node of the current sense
resistor. A current flows out of the pin, as programmed at the CLSET pin. When this pin is more negative
than the CS+ pin, the current limit comparator is triggered and the current flowing out of the pin is reduced
to two-thirds of its previous value, producing a current limit hysteresis.
17
UVLO
18
SSL
19
SSC
20
21
CORE
DACOUT
22
23
GND
OUT
24
25
VCC
RAMP
26
REG
27
28
CS+
CS–
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADP3421JRU | 制造商:AD 制造商全稱:Analog Devices 功能描述:Geyserville-Enabled DC-DC Converter Controller for Mobile CPUs |
| ADP3421JRU-REEL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADP3421JRU-REEL7 | 制造商:ON Semiconductor 功能描述: |
| ADP3422 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IMVP-II-Compliant Core Power Controller for Mobile CPUs |
| ADP3422JRU | 制造商:AD 制造商全稱:Analog Devices 功能描述:IMVP-II-Compliant Core Power Controller for Mobile CPUs |
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