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參數資料
| 型號： | ADP3422 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.35V) 8-TSSOP -40 to 110 |
| 中文描述： | 國際汽車計劃- II標準的核心電源控制器，用于移動CPU |
| 文件頁數： | 2/16頁 |
| 文件大小： | 174K |
| 代理商： | ADP3422 |
REV. 0
–2–
ADP3422–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
1
(0
≤
T
A
≤
85 C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V,
SD
= H, V
COREFB
= V
DAC
( V
DACOUT
), V
REG
= V
CS–
= V
VID
= 1.25 V, V
CPUSET
= 0 V, R
OUT
= 100 k , C
OUT
= 10 pF, C
SS
= 47 nF, R
PWRGD
= 5 k
to VCC, HYSSET, BSHIFT, DSHIFT, and FSHIFT are open,
BOM
= H,
DSLP
= H, DPRSLP = L, SWFB = L, unless otherwise noted. Current sunk
by a pin has a positive sign, sourced by a pin has a negative sign.)
to VCC, R
CLAMP
= 5.1 k
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SUPPLY-UVLO-SHUTDOWN
Normal Supply Current
UVLO Supply Current
Shutdown Supply Current
UVLO Threshold
I
CC
I
CC(UVLO)
I
CCSD
6
15
200
mA
μ
A
μ
A
SD = L
1
V
CCH
V
CCL
V
CCHYS
V
SDTH
V
CC
Rising Up, V
SS
= 0 V
V
CC
Falling, V
SS
Floating
2.95
V
V
mV
2.7
50
UVLO Hysteresis
Shutdown Threshold (CMOS Input)
V
CC
/2
POWERGOOD
Core Feedback Threshold Voltage
V
COREFBH
0.9 V < V
DAC
< 1.675 V
V
COREFB
Rising
V
COREFB
Falling
V
COREFB
Rising
V
COREFB
Falling
V
COREFB
= V
DACOUT
V
COREFB
= 0.8 V
DACOUT
V
CC
= 3.3 V
1.12 V
DAC
1.095 V
DAC
0.88 V
DAC
0.855 V
DAC
0.95 V
CC
0
1.145 V
DAC
1.12 V
DAC
0.905 V
DAC
0.88 V
DAC
V
CC
0.8
V
V
V
V
V
V
μ
s
PowerGood Output Voltage
(Open Drain Output)
Blanking Time
V
PWRGD
t
PWRGD,BLNK2
100
SOFT-START/HICCUP TIMER
Charge/Discharge Current
I
SS
V
SS
= 0.5 V
V
SS
= 0.5 V, V
CC
= 2.5 V
V
REG
= 1.25 V,
V
RAMP
= V
COREFB
= 1.27 V
V
SS
Falling
V
SS
Rising
V
RAMP
= V
COREFB
= 1.27 V
V
SS
Rising
V
SS
Falling
–16
0.6
μ
A
μ
A
Soft-Start Enable/Hiccup
Termination Threshold
V
SSEN
150
200
200
mV
mV
Soft-Start Termination/Hiccup
Enable Threshold
V
SSTERM
2.05
2.0
V
V
VID DAC
VID Input Threshold (CMOS Inputs) V
VID0...4
VID Input Current
(Internal Active Pull-up)
Output Voltage
Output Voltage Accuracy
Output Voltage Settling Time
3
0.8
10
0.7 V
CC
40
V
μ
A
I
VID0...4
VID 0...4 = L
V
DAC
V
/V
DAC
t
DADAC
See VID Code Table 1
0.600
–0.85
1.750
+0.85
V
%
μ
s
1.3
CORE COMPARATOR
Input Offset Voltage
Input Bias Current
Output Voltage
V
COREOS
I
REG
V
OUT_H
V
t
OUT_L
t
OUT_R6
t
OUT_F6
t
BLNK
V
REG
= 1.25 V
V
REG
= V
RAMP
= 1.25 V
V
CC
= 3.0 V
V
CC
= 3.6 V
±
1.5
±
0.3
mV
μ
A
V
V
ns
ns
ns
ns
ns
V
2.5
0
3.0
0.4
Propagation Delay Time
3
Rise and Fall Time
2
50
3
3
75
140
V
CC
/2
10
10
Blanking Time
OUT L-H Transition
OUT H-L Transition
Switch Feedback Threshold
(CMOS Input)
V
SWFB_TH
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