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參數(shù)資料
| 型號： | ADP3422 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.35V) 8-TSSOP -40 to 110 |
| 中文描述： | 國際汽車計劃- II標準的核心電源控制器，用于移動CPU |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 174K |
| 代理商： | ADP3422 |
REV. 0
–4–
ADP3422–SPECIFICATIONS
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
LOW-SIDE DRIVE CONTROL
Output Voltage (CMOS Output)
V
DRVLSD
DPRSLP = H
DPRSLP = L
V
= 1.5 V
DPRSLP = L
DPRSLP = H
0.4
V
CC
V
V
0.7 V
CC
Output Current
I
DRVLSD
+0.4
–0.4
mA
mA
OVER/REVERSE VOLTAGE
PROTECTION
Over-Voltage Threshold
V
COREFB,OVP
V
COREFB
Rising
V
COREFB
Falling
V
COREFB
Falling
V
COREFB
Rising
V
CLAMP
= 1.5 V
V
COREFB
= 2.2 V
V
COREFB
= V
DACOUT
= 1.25 V 1
2.0
1.8
–0.3
–0.05
2.2
V
V
V
V
Reverse-Voltage Threshold
V
COREFB,RVP
Output Current (Open Drain Output) I
CLAMP
10
μ
A
mA
4
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Two test conditions:
1. PWRGD is OK but forced to fail by applying an out-of-the-CoreGood-window voltage (V
COREFB,BAD
= 1.0 V at V
VID
= 1.25 V setting) to the COREFB pin right
after the moment that BOM or DPRSLP is asserted/deasserted. PWRGD should not fail immediately, only with the specified blanking delay time.
2. PWRGD is forced to fail (V
COREFB,BAD
= 1.0 V at V
VID
= 1.25 V setting) but gets into the CoreGood-window (V
COREFB,GOOD
= 1.25 V) right after the moment that
BOM or DPRSLP is asserted/deasserted. PWRGD should not go high immediately, only with the specified blanking delay time.
3
Guaranteed by characterization.
4
Measured from 50% of VID code transition amplitude to the point where V
DACOUT
settles within
±
1% of its steady state value.
5
40 mV p-p amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing.
6
Measured between the 30% and 70% points of the output voltage swing.
Specifications subject to change without notice.
(continued)
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