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參數資料
| 型號： | ADP3502ASU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | CDMA Power Management System |
| 中文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP64 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, PLASTIC, MS-026ABD, TQFP-64 |
| 文件頁數： | 24/36頁 |
| 文件大小： | 714K |
| 代理商： | ADP3502ASU |
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REV. 0
–24–
ADP3502
DATA INPUT/OUTPUT TIMING
5
4
3
2
1
0
1
0
7
6
5
4
3
2
1
0
ADDRESS (6-BIT)
R/W (2-BIT)
READ DATA (8-BIT)
Figure 9. Serial I/F Data Read/Write Timing
In Figure 9:
SP ADDR[5:0]: 6-Bit Address
SP CTRL[1:0]: 2-Bit Read/Write Control (01: Write, 10: Read)
SP DATA[7:0]: 8-Bit Input/Output Data
All transfers will be done MSB first.
GPIO + INT
The GPIO block has 4-channel I/O function and interrupt.
With the GPIO CONTROL register (1Ah), it is possible to
control the input or output setting of each channel individually.
The output data is set in the GPIO register (1Ch). When the
port is set in input mode, the input signal transitions from “1”
to “0” and from “0” to “1” and then generates an interrupt
signal with edge detection. The held interrupt signals are reset
by the GPIO INT RESET register (1Dh). Setting the GPIO
MASK register (1Bh) to “1” enables the interrupt of GPIO.
(Not MASKED, “1” at default in reset.)
INT Register
If the interrupt event occurs, “1,” the signal is held in this register.
INT detect and reset are synchronized at the rising edge of
CLK32K. If the interrupt event and reset signal occur at the
same time, the interrupt event has priority. The RESETIN N
signal resets the INT register (1Eh) to “0” (no INT detected),
except alarm int and pic int. The INT MASK register (1Fh)
goes to “1” (not masked). This block masks alarm int and pic int,
which generated in RTCV block, but these signals are reset with
the ALARM CONTROL register (0Dh) and PIC CONTROL
register (0Eh). The interrupt signal, INT N, is an inverted OR
signal of the value in the INT register and GPIO register.
The DATA-IN register is a port to read an interrupt status. The
input data are through the SYNC block, except the alarm signal.
Since this is for just readback purposes, the user cannot write
any data.
BATOV
RTC ALARM
CHARGER DETECT
OPT3
OPT1–
PWRONKEY–
DATA-IN REGISTER
(ADDR: 20h)
REGISTER
SYNC BLOCK
Figure 10. DATA-IN Block
Keypad Control and LED Drive
KEYPADCOL[3:0] are open-drain outputs. The
KEYPADROW[5:0] are falling edge trigger inputs (input state
transition from “1” to “0”) and generate interrupt signal and are
pulled up to LDO1. By providing four keypad-column outputs and
six keypad-row inputs, the ADP3502 can monitor up to 24 keys
with the baseband chip. Writing column outputs and reading row
inputs are controlled through a serial interface. The address of the
KEYPADROW is 19h, and KEYPADCOL is 18h. The initial
register value is “1,” which means the output of KEYPADCOL
is low. Three-stage flip-flop synchronizes signals into interrupt
circuit to 1 kHz clock.
The back-light drive is an open-drain output. The maximum
current of the internal FET is 100 mA. The initial register value
is “0,” which means the output of BLIGHT is high impedance.
Power ON Input
PWRONKEY and OPT1 have pull-up resistors, and others do
not. In addition to these inputs, other internal input signals, such
as charger detect and alarm signal (alarm int) from RTC, enable
the main and sub-LDOs of LDO1, LDO2, LDO3, LDO4, LDO6,
and LDO11. The Power ON status is held by latch data in the
delay circuit, called voltage detect delay (see 10 ms Delay section
for more information). OPT3 has a lower voltage threshold. OPT2
has a different structure than the other inputs and is pulled
down to zero by the internal signal when the phone is in Power ON
status, in order to ensure Power ON status, even if short-term
disconnection happens. Figure 11 is a block diagram of the
Power ON sequence.
INT
BLOCK
VOLTAGE DETECT DELAY
CHARGER DETECT
ALARM INT
PWRONKEY–
OPT1–
OPT2–
OPT3
140k
140k
VBAT
POWER ON
Figure 11. Power ON Input Block Diagram
相關PDF資料 |
PDF描述 |
|---|---|
| ADP3510 | Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.40V) 8-SM8 -40 to 110 |
| ADP3510ARU | Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.40V) 8-SM8 -40 to 110 |
| ADP3522 | GSM Power Management System |
| ADP3522ACP-1.8 | GSM Power Management System |
| ADP3522ACP-3 | GSM Power Management System |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADP3502ASU-REEL | 制造商:Analog Devices 功能描述:CDMA Power Management System 64-Pin TQFP T/R |
| ADP3510 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CDMA Power Management System |
| ADP3510ARU | 制造商:AD 制造商全稱:Analog Devices 功能描述:CDMA Power Management System |
| ADP3510ARU-REEL7 | 制造商:Analog Devices 功能描述: |
| ADP3522 | 制造商:AD 制造商全稱:Analog Devices 功能描述:GSM Power Management System |
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