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參數資料
| 型號： | ADP5041ACPZ-1-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 33/40頁 |
| 文件大?。?/td> | 3581K |
| 描述： | IC REG TRPL BCK/LINEAR 20-LFCSP |
| 標準包裝： | 1 |
| 拓撲： | 降壓（降壓）同步（1），線性（LDO）（2） |
| 功能： | 任何功能 |
| 輸出數： | 3 |
| 頻率 - 開關： | 3MHz |
| 電壓/電流 - 輸出 1： | 0.8 V ~ 3.8 V，1.2A |
| 電壓/電流 - 輸出 2： | 0.8 V ~ 5.2 V，300mA |
| 電壓/電流 - 輸出 3： | 0.8 V ~ 5.2 V，300mA |
| 帶 LED 驅動器： | 無 |
| 帶監控器： | 是 |
| 帶序列發生器： | 無 |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 20-LFCSP-WQ（4x4） |
| 包裝： | 標準包裝 |
| 其它名稱： | ADP5041ACPZ-1-R7DKR |
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Data Sheet
ADP5041
Rev. 0 | Page 33 of 40
Table 13. Suggested 1.0 糉 Capacitors
Vendor
Type Model
Case Size
Voltage
Rating (V)
Murata
X5R
GRM155B30J105K 0402
6.3
TDK
X5R
C1005JB0J105KT
0402
6.3
Panasonic X5R
ECJ0EB0J105K
0402
6.3
Taiyo
Yuden
X5R
LMK105BJ105MV-F 0402
10.0
Input and Output Capacitor Properties
Use any good quality ceramic capacitor with the ADP5041 as
long as it meets the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with a different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary tempe-
rature range and dc bias conditions. X5R or X7R dielectrics
with a voltage rating of 6.3 V or 10 V are recommended for best
performance. Y5V and Z5U dielectrics are not recommended
for use with any LDO because of their poor temperature and dc
bias characteristics.
Figure 110 depicts the capacitance vs. dc voltage bias characteristic
of a 0402 1 礔, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ?5% over the 40癈 to +85癈 tempera-
ture range and is not a function of package or voltage rating.
1.2
1.0
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
6
DC BIAS VOLTAGE V
Figure 110. Capacitance vs. Voltage Characteristic
Use the following equation to determine the worst-case capa-
citance, accounting for capacitor variation over temperature,
component tolerance, and voltage.
CEFF = CBIAS ?(1 TEMPCO) ?(1 TOL)
where:
C
BIAS
is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient
(TEMPCO) over 40癈 to +85癈 is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and CBIAS is 0.94 糉 at 1.8 V, as shown in Figure 110.
Substituting these values into the following equation yields:
C
EFF
= 0.94 糉 ?(1 0.15) ?(1 0.1) = 0.72 糉
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP5041, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
SUPERVISORY SECTION
Threshold Setting Resistors
Referring to Figure 105, the maximum value of R2 is not to
exceed 200 k?
Watchdog Input Current
To minimize watchdog input current (and minimize overall
power consumption), leave WDI low for the majority of the
watchdog timeout period. When driven high, WDI can draw
as much as 25 礎. Pulsing WDI low-to-high-to-low at a low
duty cycle reduces the effect of the large input current. When
WDI is unconnected, a window comparator disconnects the
watchdog timer from the reset output circuitry so that reset is
not asserted when the watchdog timer times out.
Negative-Going Transients at the Monitored Rail
To avoid unnecessary resets caused by fast power supply transients,
the ADP5041 is equipped with glitch rejection circuitry. The typical
performance characteristic in Figure 111 plots the monitored
rail voltage, V
TH
, transient duration vs. the transient magnitude.
The curve shows combinations of transient magnitude and
duration for which a reset is not generated. In this example,
with the 3.00 V threshold, a transient that goes 100 mV below
the threshold and lasts 8 祍 typically does not cause a reset, but
if the transient is any larger in magnitude or duration, a reset is
generated. In this example, the reset threshold programming
resistor values were R2 = 200 k? R1 = 1 M?(see Figure 105).
900
800
700
600
500
400
300
200
100
0
0.1
1
10
100
COMPARATOR OVERDRIVE (% OF V
TH
)
Figure 111. Maximum VTH Transient Duration vs. Reset
Threshold Overdrive
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相關代理商/技術參數 |
參數描述 |
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| ADP5041CP-1-EVALZ | 功能描述:ADP5041 - DC/DC, Step Down with LDO 3, Non-Isolated Outputs Evaluation Board 制造商:analog devices inc. 系列:- 零件狀態:有效 主要用途:DC/DC，LDO 步降 輸出和類型:3，非隔離 功率 - 輸出:- 電壓 - 輸出:- 電流 - 輸出:1.2A，300mA，300mA 電壓 - 輸入:2.3 V ~ 5.5 V 穩壓器拓撲:降壓 頻率 - 開關:3MHz 板類型:完全填充 所含物品:板 使用的 IC/零件:ADP5041 標準包裝:1 |
| ADP5042 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Micro PMU with 0.8 A Buck, Two 300 mA LDOs Supervisory, Watchdog and Manual Reset |
| ADP5042ACPZ-1 | 制造商:Analog Devices 功能描述:PMU 2 LDO DUAL BUCK 20LFCSP 制造商:Analog Devices 功能描述:PMU, 2 LDO, DUAL BUCK, 20LFCSP |
| ADP5042ACPZ-1-R7 | 功能描述:IC REG TRPL BCK/LINEAR 20LFCSP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩壓器 - 線性 + 切換式 系列:- 標準包裝:2,500 系列:- 拓撲:降壓（降壓）同步（3），線性（LDO）（2） 功能:任何功能 輸出數:5 頻率 - 開關:300kHz 電壓/電流 - 輸出 1:控制器 電壓/電流 - 輸出 2:控制器 電壓/電流 - 輸出 3:控制器 帶 LED 驅動器:無 帶監控器:無 帶序列發生器:是 電源電壓:5.6 V ~ 24 V 工作溫度:-40°C ~ 85°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| ADP5042ACPZ-2 | 制造商:Analog Devices 功能描述:PMU 2 LDO DUAL BUCK 20LFCSP 制造商:Analog Devices 功能描述:PMU, 2 LDO, DUAL BUCK, 20LFCSP |
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