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參數資料
| 型號： | ADSP-21366SBBC-ENG |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, MBGA-136 |
| 文件頁數： | 17/54頁 |
| 文件大小： | 559K |
| 代理商： | ADSP-21366SBBC-ENG |
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ADSP-21365/6
Preliminary Technical Data
Rev. PrA
|
Page 17 of 54
|
September 2004
(PLL). This PLL-based clocking minimizes the skew between
the system clock (CLKIN) signal and the processor’s internal
clock (the clock source for the parallel port logic and I/O pads).
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control (
Table 8
).
Figure 5
shows Core to CLKIN ratios of 6:1, 16:1 and 32:1 with
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the
ADSP-
2136x SHARC Processor Programming Reference
.
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 38 on page 43
under Test Conditions for voltage refer-
ence levels.
Switching Characteristics
specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements
apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Table 8. ADSP-21365/6 CLKOUT and CCLK Clock
Generation Operation
Timing
Requirements
CLKIN
CCLK
Description
Calculation
Input Clock
Core Clock
1/t
CK
1/t
CCLK
Table 9. Clock Periods
Timing
Requirements
t
CK
t
CCLK
t
PCLK
t
SCLK
t
SPICLK
Description
1
1
where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT
CLKDIV)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register)
DAI_Px = Serial Port Clock
SPICLK = SPI Clock
CLKIN Clock Period
(Processor) Core Clock Period
(Peripheral) Clock Period = 2 × t
CCLK
Serial Port Clock Period = (t
PCLK
) × SR
SPI Clock Period = (t
PCLK
) × SPIR
Figure 5. Core Clock and System Clock Relationship to CLKIN
CLKIN
CCLK
(CORECLOCK)
PLLILCLK
XTAL
XTAL
OSC
PLL
6:1, 16:1,
32:1
CLKOUT
CLK-CFG[1:0]
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相關代理商/技術參數 |
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|---|---|
| ADSP-21366SBBCZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366SBSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366SBSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366SCSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366SCSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
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