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參數資料
| 型號： | ADSP-2171BST-133 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 24-BIT, 16.67 MHz, OTHER DSP, PQFP128 |
| 封裝： | PLASTIC, TQFP-128 |
| 文件頁數： | 5/52頁 |
| 文件大小： | 664K |
| 代理商： | ADSP-2171BST-133 |
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ADSP-2171/ADSP-2172/ADSP-2173
REV. A
–5–
Interrupts
T he interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
T he ADSP-217x provides up to three external interrupt input
pins,
IRQ0
,
IRQ1
and
IRQ2
.
IRQ2
is always available as a dedi-
cated pin; SPORT 1 may be reconfigured for
IRQ0
,
IRQ1
, and
the flags. T he ADSP-217x also supports internal interrupts from
the timer, the host interface port, the two serial ports, software,
and the powerdown control circuit. T he interrupt levels are in-
ternally prioritized and individually maskable (except power-
down and reset). T he input pins can be programmed to be
either level- or edge-sensitive. T he priorities and vector ad-
dresses of all interrupts are shown in T able II, and the interrupt
registers are shown in Figure 2.
Interrupts can be masked or unmasked with the IMASK regis-
ter. Individual interrupt requests are logically ANDed with the
bits in IMASK ; the highest priority unmasked interrupt is then
selected.T he powerdown interrupt is nonmaskable.
T he ADSP-217x masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. T his does not affect autobuffering.
T he interrupt control register, ICNT L, allows the external in-
terrupts to be either edge- or level-sensitive. Interrupt routines
can either be nested with higher priority interrupts taking prece-
dence or processed sequentially.
T he IFC register is a write-only register used to force and clear
interrupts generated from software.
T able II. Interrupt Priority & Interrupt Vector Addresses
Interrupt Vector
Address (Hex)
Source of Interrupt
Reset (or Power-Up with PUCR = 1)
Powerdown (Nonmaskable)
IRQ2
HIP Write
HIP Read
SPORT 0 T ransmit
SPORT 0 Receive
Software Interrupt 1
Software Interrupt 0
SPORT 1 T ransmit or
IRQ1
SPORT 1 Receive or
IRQ0
T imer
0000
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028
(
Highest Priority
)
(
Lowest Priority
)
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling.
T he stacks are twelve levels deep to allow interrupt nesting.
T he following instructions allow global enable or disable servic-
ing of the interrupts (including powerdown), regardless of the
state of IMASK . Disabling the interrupts does not affect
autobuffering.
ENA INT S;
DIS INT S;
When you reset the processor, the interrupt servicing is enabled.
Figure 2. Interrupt Registers
Timer
SPORT1 Receive or IRQ0
SPORT1 Transmit or IRQ1
Software 0
Software 1
SPORT0 Receive
SPORT0 Transmit
IRQ2
IRQ2
SPORT0 Transmit
SPORT0 Receive
Software 1
Software 0
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
INTERRUPT FORCE
INTERRUPT CLEAR
IFC
7
9
8
6
5
4
3
2
1
0
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IRQ0 Sensitivity
IRQ1 Sensitivity
IRQ2 Sensitivity
Interrupt Nesting
1 = enable, 0 = disable
0
ICNTL
2
1 = edge
0 = level
4
3
1
0
10
11
12
13
14
15
9
8
7
6
5
4
3
2
1
0
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
IMASK
1 = enable, 0 = disable
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Timer
IRQ0 or SPORT1 Receive
IRQ1 or SPORT1 Transmit
Software 0
Software 1
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