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參數資料
| 型號： | ADSP-2185L |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LM2941/LM2941C 1A Low Dropout Adjustable Regulator; Package: CERDIP; No of Pins: 16; Qty per Container: 25; Container: Rail |
| 中文描述： | DSP的微機 |
| 文件頁數： | 19/31頁 |
| 文件大?。?/td> | 223K |
| 代理商： | ADSP-2185L |
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ADSP-2185L
–19–
REV. A
Parameter
Min
Max
Unit
Interrupts and Flag
Timing Requirements
:
t
IFS
t
IFH
IRQx
, FI, or PFx Setup before CLKOUT Low
1, 2, 3, 4
IRQx
, FI, or PFx Hold after CLKOUT High
1, 2, 3, 4
0.25t
CK
+ 15
0.25t
CK
ns
ns
Switching Characteristics:
t
FOH
t
FOD
Flag Output Hold after CLKOUT Low
5
Flag Output Delay from CLKOUT Low
5
0.25t
CK
– 7
ns
ns
0.5t
CK
+ 6
NOTES
1
If
IRQx
and FI inputs meet t
and t
setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)
2
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx
=
IRQ0
,
IRQ1
,
IRQ2
,
IRQL0
,
IRQL1
,
IRQE
.
4
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5
Flag outputs = PFx, FL0, FL1, FL2, Flag_out.
t
FOD
t
FOH
t
IFH
t
IFS
CLKOUT
FLAG
OUTPUTS
IRQx
FI
PFx
Figure 20. Interrupts and Flags
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