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參數資料
| 型號： | ADSP-BF532 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | Blackfin Embedded Processor |
| 中文描述： | Blackfin嵌入式處理器 |
| 文件頁數： | 41/56頁 |
| 文件大小： | 671K |
| 代理商： | ADSP-BF532 |
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. 0
|
Page 41 of 56
|
March 2004
POWER DISSIPATION
Total power dissipation has two components: one due to inter-
nal circuitry (P
INT
) and one due to the switching of external
output drivers (P
EXT
).
Table 32
shows the power dissipation for
internal circuitry (V
DDINT
). Internal power dissipation is depen-
dent on the instruction execution sequence and the data
operands involved.
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
Number of output pins (O) that switch during each cycle
Maximum frequency (f) at which they can switch
Their load capacitance (C)
Their voltage swing (V
DDEXT
)
The external component is calculated using:
The frequency f includes driving the load high and then back
low. For example: DATA15–0 pins can drive high and low at a
maximum rate of 1/(2
t
SCLK
) while in SDRAM burst mode.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
Note that the conditions causing a worst-case P
EXT
differ from
those causing a worst-case P
INT
. Maximum P
INT
cannot occur
while 100% of the output pins are switching from all ones (1s) to
all zeros (0s). Note, as well, that it is not common for an applica-
tion to have 100% or even 50% of the outputs switching
simultaneously.
Table 32. Internal Power Dissipation
1
1
See EE-229: Estimating Power for ADSP-BF533 Blackfin Processors.
2
I
DD
data is specified for typical process parameters. All data at 25oC.
3
Processor executing 75% dual Mac, 25% ADD with moderate data bus activity.
4
See the
ADSP-BF53x Blackfin Processor Hardware Reference Manual
for defini-
tions of Sleep and Deep Sleep operating modes.
5
Measured at V
DDEXT
= 3.65V with voltage regulator off (V
DDINT
= 0V).
6
Measured at V
DDRTC
= 3.3V at 25oC.
Test Conditions
2
f
CCLK
=
50 MHz
V
DDINT
=
0.8 V
26
16
14
50
30
Parameter
f
CCLK
=
400 MHz
V
DDINT
=
1.2 V
160
37
31
f
CCLK
=
500 MHz
V
DDINT
=
1.2 V
190
37
31
f
CCLK
=
600 MHz
V
DDINT
=
1.2 V
220
37
31
Unit
I
DDTYP
3
I
DDSLEEP
4
I
DDDEEPSLEEP
4
I
DDHIBERNATE
5
I
DDRTC
6
mA
mA
mA
A
A
P
EXT
O
C
×
V
2
DD
×
f
×
=
P
TOTAL
P
EXT
I
DD
V
DDINT
×
(
)
+
=
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