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參數資料
型號: ADSP21020
廠商: Analog Devices, Inc.
元件分類: 數字信號處理
英文描述: 32/40-Bit IEEE Floating-Point DSP Microprocessor
中文描述: 32/40 IEEE浮點DSP微處理器
文件頁數: 8/32頁
文件大小: 425K
代理商: ADSP21020
ADSP-21020
REV. C
–8–
Table II. Condition and Termination Codes
Name
Description
eq
ne
ge
lt
le
gt
ac
not ac
av
not av
mv
not mv
ms
not ms
sv
not sv
sz
not sz
flag0_in
not flag0_in
flag1_in
not flag1_in
flag2_in
not flag2_in
flag3_in
not flag3_in
tf
not tf
lce
not lce
forever
true
ALU equal to zero
ALU not equal to zero
ALU greater than or equal to zero
ALU less than zero
ALU less than or equal to zero
ALU greater than zero
ALU carry
Not ALU carry
ALU overflow
Not ALU overflow
Multiplier overflow
Not multiplier overflow
Multiplier sign
Not multiplier sign
Shifter overflow
Not shifter overflow
Shifter zero
Not shifter zero
Flag 0
Not Flag 0
Flag 1
Not Flag l
Flag 2
Not Flag 2
Flag 3
Not Flag 3
Bit test flag
Not bit test flag
Loop counter expired (DO UNTIL)
Loop counter not expired (IF)
Always False (DO UNTIL)
Always True (IF)
In a conditional instruction, the execution of the entire instruction is based on
the specified condition.
IMMEDIATE MOVE INSTRUCTIONS
14a. DM(<addr32>)
PM(<addr24>)
14b. ureg =
= ureg
;
DM(<addr32>)
PM(<addr24>)
= ureg;
;
15a. DM(<data32>, Ia)
PM(< data24>, Ic)
15b. ureg =
DM(<data32>, Ia)
PM(<data24>, Ic)
= <data32>;
;
16.
DM(Ia, Mb)
PM(Ic, Md)
ureg = <data32>;
17.
MISCELLANEOUS INSTRUCTIONS
18. BIT
SET
CLR
TGL
TST
XOR
(Ia, <data32>)
|
;
(Ic, <data32>)
|
(Ia, <data32>)
LOOP
sreg <data32>;
19a. MODIFY
19b. BITREV
20.
|
PUSH
|
POP
21. NOP ;
22. IDLE ;
;
,
PUSH
POP
STS
;
Table I. Syntax Notation Conventions
Notation
Meaning
UPPERCASE
Explicit syntax—assembler keyword (nota-
tion only; assembler is not case-sensitive
and lowercase is the preferred programming
convention)
Instruction terminator
Separates parallel operations in an
instruction
Optional part of instruction
List of options (choose one)
n
-bit immediate data value
n
-bit immediate address value
n
-bit immediate PC-relative address value
ALU, multiplier, shifter or multifunction
operation (from Tables IV-VII)
Shifter immediate operation
(from Table VI)
Status condition (from Table II)
Termination condition (from Table II)
Universal register (from Table III)
System register (from Table III)
R15-R0, F15-F0; register file location
I7-I0; DAG1 index register
M7-M0; DAG1 modify register
I15-I8; DAG2 index register
M15-M8; DAG2 modify register
;
,
italics
| between lines |
<data
n
>
<addr
n
>
<reladdr
n
>
compute
shiftimm
condition
termination
ureg
sreg
dreg
Ia
Mb
Ic
Md
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相關代理商/技術參數
參數描述
ADSP-21020 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
ADSP-21020BG-100 制造商:AD 制造商全稱:Analog Devices 功能描述:32/40-Bit IEEE Floating-Point DSP Microprocessor
ADSP-21020BG-120 制造商:AD 制造商全稱:Analog Devices 功能描述:32/40-Bit IEEE Floating-Point DSP Microprocessor
ADSP-21020BG-80 制造商:AD 制造商全稱:Analog Devices 功能描述:32/40-Bit IEEE Floating-Point DSP Microprocessor
ADSP-21020KG-100 制造商:AD 制造商全稱:Analog Devices 功能描述:32/40-Bit IEEE Floating-Point DSP Microprocessor
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