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參數(shù)資料
| 型號： | ADSP2181 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | DSP微機 |
| 文件頁數(shù)： | 6/32頁 |
| 文件大小： | 290K |
| 代理商： | ADSP2181 |
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REV. D
ADSP-2181
–6–
When the
IDLE (n)
instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in-
coming interrupts. T he one-cycle response time of the standard
idle state is increased by
n
, the clock divisor. When an enabled
interrupt is received, the ADSP-2181 will remain in the idle
state for up to a maximum of
n
processor cycles (
n
= 16, 32, 64
or 128) before resuming normal operation.
When the
IDLE (n)
instruction is used in systems that have an
externally generated serial clock (SCLK ), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of
n
processor cycles).
SY ST E M INT E RFACE
Figure 2 shows a typical basic system configuration with the
ADSP-2181, two serial devices, a byte-wide EPROM, and op-
tional external program and data overlay memories. Program-
mable wait state generation allows the processor to connect
easily to slow peripheral devices. T he ADSP-2181 also provides
four external interrupts and two serial ports or six external inter-
rupts and one serial port.
1/2xOR
CRYSTAL
SERIAL
SERIAL
16
A0-A21
DATA
CS
BYTE
MEMORY
I/O SPACE
(PERIPHERALS)
2048 LOCATIONS
CS
DATA
ADDR
DATA
ADDR
OVERLAY
MEMORY
PM TWO 8K
DM TWO 8K
D
23-0
A
13-0
D
23-8
A
10-0
D
15-8
D
23-16
A
13-0
14
24
SCLK1
RFS1 OR
IRQ0
IRQ1
TFS1 OR
SCLK0
SPORT0
IAD15-0
IDMA PORT
IRD
IACK
FL0-2
PF0-7
CLKIN
XTAL
ADDR13-0
DATA23-0
BMS
IOMS
ADSP-2181
RD
WR
IRQ2
IRQE
IRQL0
IRQL1
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
ISYOR
m
CONTROLLER
Figure 2. ADSP-2181 Basic System Configuration
Clock Signals
T he ADSP-2181 can be clocked by either a crystal or a T T L-
compatible clock signal.
T he CLK IN input cannot be halted, changed during operation
or operated below the specified frequency during normal opera-
tion. T he only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual,
Third Edition
, for detailed
information on this power-down feature.
If an external clock is used, it should be a T T L-compatible
signal running at half the instruction rate. T he signal is con-
nected to the processor’s CLK IN input. When an external clock
is used, the X T AL input
must
be left unconnected.
T he ADSP-2181 uses an input clock with a frequency equal to
half the instruction rate; a 20.00 MHz input clock yields a 25 ns
processor cycle (which is equivalent to 40 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLK OUT signal when enabled.
Because the ADSP-2181 includes an on-chip oscillator circuit,
an external crystal may be used. T he crystal should be connected
across the CLK IN and X T AL pins, with two capacitors connected
as shown in Figure 3. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used.
A clock output (CLK OUT ) signal is generated by the processor
at the processor’s cycle rate. T his can be enabled and disabled
by the CLK ODIS bit in the SPORT 0 Autobuffer Control
Register.
CLKIN
CLKOUT
XTAL
DSP
Figure 3. External Crystal Connections
Reset
T he
RESET
signal initiates a master reset of the ADSP-2181.
T he
RESET
signal must be asserted during the power-up se-
quence to assure proper initialization.
RESET
during initial
power-up must be held long enough to allow the internal clock
to stabilize. If
RESET
is activated any time after power-up, the
clock continues to run and does not require stabilization time.
T he power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
DD
is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLK IN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the
RESET
signal should be held low. On
any subsequent resets, the
RESET
signal must meet the mini-
mum pulse width specification, t
RSP
.
T he
RESET
input contains some hysteresis; however, if you use
an RC circuit to generate your
RESET
signal, the use of an
external Schmidt trigger is recommended.
T he master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MST AT
register. When
RESET
is released, if there is no pending bus
request and the chip is configured for booting (MMAP = 0), the
boot-loading sequence is performed. T he first instruction is
fetched from on-chip program memory location 0x0000 once
boot loading completes.
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PDF描述 |
|---|---|
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| ADSP-2183KST-160 | DSP Microcomputer |
| ADSP-2183KCA-210 | DSP Microcomputer |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-2181 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2181BS-115 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 28.8MHz 28.8MIPS 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:DSP W/LARGE RAM, 28.8MIPS I GRDE, PQFP - Bulk |
| ADSP-2181BS-133 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 33.3MHz 33.3MIPS 128-Pin MQFP 制造商:Analog Devices 功能描述:IC MICROCOMPUTER DSP |
| ADSP-2181BS-160 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| ADSP2181BST115 | 制造商:AD 功能描述:2181 ANALOG |
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