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參數資料
| 型號： | ADT7463ARQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | dB COOL Remote Thermal Controller and Voltage Monitor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO24 |
| 封裝： | MO-137AE, QSOP-24 |
| 文件頁數： | 21/53頁 |
| 文件大小： | 719K |
| 代理商： | ADT7463ARQ |
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REV. 0
ADT7463
–21–
be masked out to prevent
SMBALERT
interrupts. Note that
masking an interrupt source only prevents the
SMBALERT
output from being asserted; the appropriate Status bit will get
set as normal.
Interrupt Mask Register 1 (Reg. 0x74)
Bit 7 (OOL) = 1,
masks
SMBALERT
for any alert condition
flagged in Status Register 2.
Bit 6 (R2T) = 1,
masks
SMBALERT
for Remote 2 Temperature.
Bit 5 (LT) = 1,
masks
SMBALERT
for Local Temperature.
Bit 4 (R1T) = 1,
masks
SMBALERT
for Remote 1 Temperature.
Bit 3 (5 V) = 1,
masks
SMBALERT
for 5 V channel.
Bit 2 (V
CC
) = 1,
masks
SMBALERT
for V
CC
channel.
Bit 1 (V
CCP
) = 1,
masks
SMBALERT
for V
CCP
channel.
Bit 0 (2.5 V) = 1,
masks
SMBALERT
for 2.5 V channel.
Interrupt Mask Register 2 (Reg. 0x75)
Bit 7 (D2) = 1,
masks
SMBALERT
for Diode 2 errors.
Bit 6 (D1) = 1,
masks
SMBALERT
for Diode 1 errors.
Bit 5 (FAN4) = 1,
masks
SMBALERT
for Fan 4 failure. If the
TACH4 pin is being used as the
THERM
input, this bit masks
SMBALERT
for a
THERM
event.
Bit 4 (FAN3) = 1,
masks
SMBALERT
for Fan 3.
Bit 3 (FAN2) = 1,
masks
SMBALERT
for Fan 2.
Bit 2 (FAN1) = 1,
masks
SMBALERT
for Fan 1.
Bit 1 (OVT) = 1,
masks
SMBALERT
for overtemperature
(exceeding
THERM
limits).
Bit 0 (12V/VC) = 1,
masks
SMBALERT
for 12 V channel or
for a VID Code change, depending on the function used.
Enabling the
SMBALERT
Interrupt Output
The
SMBALERT
interrupt function is disabled by default. Pin
10 or Pin 22 can be reconfigured as an
SMBALERT
output to
signal out-of-limit conditions.
CONFIGURING PIN 10 AS
SMBALERT
OUTPUT
REGISTER
Config Reg 3 (Reg. 0x78)
BIT SETTING
<0> ALERT = 1
CONFIGURING PIN 22 AS
SMBALERT
OUTPUT
REGISTER
Config Reg 4 (Reg. 0x7D)
Therm Input
The ADT7463 has an internal timer to measure
THERM
asser-
tion time. For example, the
THERM
input may be connected
to
the
PROCHOT
output of a Pentium 4 CPU and measure
system performance.
The
THERM
input may also be con-
nected to the output of a trip point temperature sensor.
The timer is started on the assertion of the ADT7463’s
THERM
input, and stopped on the negation of the pin. The
timer counts
THERM
times cumulatively, i.e. the timer
resumes counting on the next
THERM
assertion. The
THERM
timer will continue to accumulate
THERM
assertion times until
the timer is read (it is cleared on read) or until it reaches full
BIT SETTING
<0> AL2.5V = 1
scale. If the counter reaches full scale, it will stop at that reading
until cleared.
The 8-bit
THERM
Timer register (Reg. 0x79) is designed such
that Bit 0 will get set to 1 on the first
THERM
assertion. Once
the cumulative
THERM
assertion time has exceeded 45.52 ms,
Bit 1 of the
THERM
timer gets set, and Bit 0 now becomes the
LSB of the timer with a resolution of 22.76 ms.
THERM
TIMER
(REG. 0x79)
THERM
0 0 0 0 0 0 1 0
7 6 5 4 3 2 1 0
THERM
ASSERTED
22.76ms
THERM
ACCUMULATE
THERM
LOW
ASSERTION TIMES
THERM
ASSERTED
45.52ms
0 0 0 0 0 1 0 1
7 6 5 4 3 2 1 0
THERM
ASSERTED
113.8ms
(91.04ms + 22.76ms)
THERM
TIMER
(REG. 0x79)
THERM
TIMER
(REG. 0x79)
THERM
ACCUMULATE
THERM
LOW
ASSERTION TIMES
0 0 0 0 0 0 0 1
7 6 5 4 3 2 1 0
Figure 25. Understanding the
THERM
Timer
Figure 25 illustrates how the
THERM
timer behaves as the
THERM
input is asserted and negated. Bit 0 gets set on the
first
THERM
assertion detected. This bit remains set until
such time as the cumulative
THERM
assertions exceed
45.52 ms. At this time, Bit 1 of the
THERM
timer gets set,
and Bit 0 is cleared. Bit 0 now reflects timer readings with a
resolution of 22.76 ms.
When using the
THERM
timer, be aware of the following:
After a
THERM
timer read (Reg. 0x79):
a) The contents of the timer get cleared on read.
b) The F4P bit (Bit 5) of Status Register 2 needs to be cleared
(assuming the
THERM
limit has been exceeded).
If the
THERM
timer is read during a
THERM
assertion, then
the following will happen:
a) The contents of the timer are cleared.
b) Bit 0 of the
THERM
timer is set to 1 (since a
THERM
assertion is occurring).
c) The
THERM
timer increments from zero.
d) If the
THERM
limit (Reg. 0x7A) = 0x00, then the F4P bit
gets set.
Generating
SMBALERT
Interrupts from
THERM
Events
The ADT7463 can generate
SMBALERT
s when a program-
mable
THERM
limit has been exceeded. This allows the
systems designer to ignore brief, infrequent
THERM
assertions,
while capturing longer
THERM
events. Register 0x7A is the
THERM
Limit Register. This 8-bit register allows a limit from
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