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參數資料
| 型號： | ADUC7027AST62 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 32-BIT, FLASH, 45.5 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, LQFP-80 |
| 文件頁數： | 59/80頁 |
| 文件大?。?/td> | 840K |
| 代理商： | ADUC7027AST62 |
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Preliminary Technical Data
ADuC702x Series
Rev. PrB | Page 59 of 80
I
2
C COMPATIBLE INTERFACES
The ADuC702x supports two fully licensed
*
I
2
C interfaces. The I
2
C
interfaces are both implemented as a full hardware master and
slave interface. The two I
2
C interfaces being identical, this
document will describe only I
2
C0 in detail.
The two pins used for data transfer, SDA and SCL are
configured in a Wired-AND format that allows arbitration in a
multi-master system.
The I
2
C bus peripheral’s addresses in the I
2
C bus system is
programmed by the user. This ID can be modified at any time
while a transfer is not in progress. The user can configure the
interface to respond to four slave addresses.
The transfer sequence of a I
2
C system consists of a master device
initiating a transfer by generating a START condition while the
bus is idle. The master transmits the address of the slave device
and the direction of the data transfer in the initial address
transfer. If the master does not loose arbitration and the slave
acknowledges then the data transfer is initiated. This continues
until the master issues a STOP condition and the bus becomes
idle.
The I
2
C peripheral master and slave functionality are
independent and may be active simultaneously.
A slave is activated when a transfer has been initiated on the
bus. If it is not being addressed it will remain inactive until
another transfer is initiated. This also allows a master device
which looses arbitration to respond as a slave in the same cycle.
Serial Clock Generation
The I
2
C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
Fast mode (400 kHz) or Standard mode (100 kHz).
The bit-rate is defined in the I2C0DIVH and I2C0DIVL
MMRs as follow:
)
0
2
0
2
2
×
2
DIVL
C
I
DIVH
C
I
f
f
coreclock
k
serialcloc
+
+
=
Slave addresses
The registers I2C0ID0, I2C0ID1, I2C0ID2 and I2C0ID3
contain the device IDs. The device compares the four I2C0IDx
registers to the address byte. The 7 most significant bits of
either ID register must be identical to that of the 7 most
significant bits of the first address byte received to be correctly
addressed. The LSB of the ID registers, transfer direction bit, is
ignored in the process of address recognition.
I
2
C registers description
The I
2
C peripheral interface consists on 17 8-bit MMRs:
-
I2C0CFG:
configuration register described Table 48
-
I2C0DIVH, I2C0DIVL:
clock divider registers
-
I2C0SRX, I2C0STX, and I2C0SSTA:
respectively receive,
transmit and status register for the slave channel. The status
register is described Table 49.
-
I2C0ID0, I2C0ID1, I2C0ID2 and I2C0ID3:
slave address
device ID register
-
I2C0MRX, I2C0MTX, and I2C0MSTA:
respectively receive,
transmit and status register for the master channel. The status
register is described Table 50.
-
I2C0CNT:
Master receive data count register. If a master read
transfer sequence is initiated, the I2C0CNT register denotes
the number of bytes to be read from the slave device.
-
I2C0ADR:
master address byte register. The I2C0ADR value
is the address of the device the master wants to communicate
with, it will be transmitted automatically at the start of a
master transfer sequence if there is no valid data in the
I2C0MTX register when setting the master enable bit.
-
I2C0ALT:
hardware general call ID register, used in slave
mode
Table 48: I2C0CFG MMR Bit Descriptions
Bit
7
Description
Master serial clock enable bit
Set
by user to enable generation of the serial clock in master mode
Cleared
by user to disable serial clock in master mode
Loop back enable bit
Set
by user to internally connect the transition to the reception, to test user software
Cleared
by user to operate in normal mode
START back-off disable bit
Set
by user in multi-master mode. If losing arbitration the master will try to transmit again straight away
Cleared
by user to enable START back-off. The master after losing arbitration will wait before trying to transmit again
Hardware general call enable (bit 3 must be set)
Set
by user to enable hardware general call
Cleared
by user to disable hardware general call
6
5
4
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