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參數資料
| 型號： | ADUC7027AST62 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 32-BIT, FLASH, 45.5 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, LQFP-80 |
| 文件頁數： | 70/80頁 |
| 文件大小： | 840K |
| 代理商： | ADUC7027AST62 |
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ADuC702x Series
Preliminary Technical Data
value must be written to T3ICLR before the expiration period.
This reloads the counter with T3LD and begins a new timeout
period.
Rev. PrB | Page 70 of 80
As soon watchdog mode is entered, T3LD and T3CON are
write-protected. These two registers can not be modified until a
reset clears the watchdog enable bit and causes Timer3 to exit
watchdog mode.
Timer3 interface:
It consists in four MMRS:
-
T3LD
and
T3VAL
are 16-bit registers (bit 0 to 15) and hold
16-bit unsigned integers. T0VAL is read-only.
-
T3CLRI
is an 8-bit register. Writing any value to this register
will clear the timer3 interrupt in normal mode or will reset a
new timeout period in watchdog mode.
-
T3CON
is the configuration MMR described in Table 63.
Secure bit clear (watchdog mode only):
The secure clear bit is provided for a higher level of protection.
When set, a specific sequential value must be written to
T3ICLR to avoid a watchdog reset. The value is a sequence
generated by the 8-bit LFSR (Linear Feedback Shift Register)
polynomial = X8 + X6 + X5 + X + 1 as shown Figure 32. The
initial value or seed is written to T3ICLR before entering
watchdog mode. After entering watchdog mode, a write to
T3ICLR must match this expected value. If it matches, the
LFSR is advanced to the next state when the counter reload
happens. If it fails to match the expected state, reset is
immediately generated, even if the count has not yet expired.
The value 0x00 should not be used as an initial seed due to the
properties of the polynomial. The value 0x00 will always be
guaranteed to force an immediate reset. The value of the LFSR
can not be read; it must be tracked/generated in software.
D
Q
6
D
Q
0
D
Q
1
D
Q
2
D
Q3
D
Q
7
D
Q
4
D
Q
5
Clock
Figure 32: 8-bit LFSR
Example of sequence:
1) entered initial seed in T3ICLR, 0xAA, before starting timer 3
in watchdog mode
2) enter 0xAA in T3ICLR, timer 3 is reloaded
3) enter 0x37 in T3ICLR, timer 3 is reloaded
4) enter 0x6E in T3ICLR, timer 3 is reloaded
5) enter 0x66. 0xDC was expected, the watchdog reset the chip.
Table 63: T3CON MMR Bit Descriptions
Bit
31-9
8
Description
Reserved
Count up:
Set by user for timer 3 to count up
Cleared by user for timer 3 to count down. by default
Timer3 enable bit:
Set by user to enable timer 3
Cleared by user to disable timer 3. by default.
Timer 3 mode:
Set by user to operate in periodic mode
Cleared by user to operate in free-running mode. Default mode
Watchdog mode enable bit:
Set by user to enable watchdog mode
Cleared by user to disable watchdog mode. by default.
Secure Clear bit:
Set by user to use the secure clear option
Cleared by user to disable the secure clear option. by default.
Prescale:
00
Source clock / 1 by default
01
Source clock / 16
10
Source clock / 256
11
Undefined. Equivalent to 00
Watchdog IRQ option bit:
Set by user to produce an IRQ instead of a reset when the watchdog reaches 0
Cleared by user to disable the IRQ option.
Reserved
7
6
5
4
3-2
1
0
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