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參數資料
| 型號： | ADUC814BRU-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Circular Connector; No. of Contacts:61; Series:LJT07R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:25-61 |
| 中文描述： | 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | 4.40 X 9.70 MM, MO-153AE, TSSOP-28 |
| 文件頁數： | 46/72頁 |
| 文件大小： | 846K |
| 代理商： | ADUC814BRU-REEL7 |
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ADuC814
I
2
C COMPATIBLE INTERFACE
The ADuC814 supports a 2-wire serial interface mode that is
I
2
C compatible. The I
2
C compatible interface shares its pins with
the on-chip SPI interface, and therefore the user can enable only
one interface or the other at any given time (see the SPE bit in
SPICON SFR, Table 18). Application Note uC001 describes the
operation of this interface as implemented, and is available on
the MicroConverter website at
. Rev. A | Page 46 of 72
SDATA
(Pin 24) Serial Data I/O
SCLOCK
(Pin 25) Serial Clock
Three SFRs are used to control the I
2
C compatible interface.
I2CCON
SFR Address
Power-On Default
Bit Addressable
I
2
C Control Register
E8H
00H
Yes
MDO
MDE
MCO
MDI
I2CM
I2CRS
I2CTX
I2CI
Table 19. I2CCON SFR Bit Designations
Bit No.
Name
7
MDO
Description
I
2
C Software Master Data Output Bit (Master Mode Only).
This data bit is used to implement a master I
2
C transmitter interface in software. Data written to this bit is output on
the SDATA pin if the data output enable (MDE) bit is set.
I
2
C Software Master Data Output Enable Bit (Master Mode Only).
Set by the user to enable the SDATA pin as an output (Tx).
Cleared by the user to enable SDATA pin as an input (Rx).
I
2
C Software Master Clock Output Bit (Master Mode Only).
This data bit is used to implement a master I
2
C transmitter interface in software. Data written to this bit is output on
the SCLOCK pin.
I
2
C Software Master Data Input Bit (Master Mode Only).
This data bit is used to implement a master I
2
C receiver interface in software. Data on the SDATA pin is latched into
this bit on SCLOCK if the data output enable (MDE) bit is 0.
I
2
C Master/Slave Mode Bit.
Set by the user to enable I
2
C software master mode.
Cleared by the user to enable I
2
C hardware slave mode.
I
2
C Reset Bit (Slave Mode Only).
Set by the user to reset the I
2
C interface.
Cleared
by the user code for normal I
2
C operation.
I
2
C Direction Transfer Bit (Slave Mode Only).
Set by the MicroConverter if the interface is transmitting.
Cleared by the MicroConverter if the interface is receiving.
I
2
C Interrupt Bit (Slave Mode Only).
Set by the MicroConverter after a byte has been transmitted or received.
Cleared automatically when user code reads the I2CDAT SFR (see the I2CDAT SFR description that follows).
6
MDE
5
MCO
4
MDI
3
I2CM
2
I2CRS
1
I2CTX
0
I2CI
I2CADD
Function
I
2
C Address Register
Holds the I
2
C peripheral address for the part. It may be overwritten by the user code. Application Note uC001 at
www.analog.com/microconverter describes the format of the 7-bit address in detail.
9BH
55H
No
SFR Address
Power-On Default
Bit Addressable
I2CDAT
Function
I
2
C Data Register
The I2CDAT SFR is written to by the user code to transmit data over the I
2
C interface, or it is read by the user
code to read data just received via the I
2
C interface. Accessing the I2CDAT register automatically clears any
pending I
2
C interrupts and the I2CI bit in the I2CCON SFR.
9AH
00H
No
SFR Address
Power-On Default
Bit Addressable
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