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參數資料
| 型號： | ADUC814BRU-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Circular Connector; No. of Contacts:61; Series:LJT07R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:25-61 |
| 中文描述： | 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | 4.40 X 9.70 MM, MO-153AE, TSSOP-28 |
| 文件頁數： | 53/72頁 |
| 文件大小： | 846K |
| 代理商： | ADUC814BRU-REEL7 |
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ADuC814
UART SERIAL INTERFACE
The serial port is full duplex, meaning it can transmit and
receive simultaneously. It is also receive-buffered, meaning it
can begin receiving a second byte before a previously received
byte has been read from the receive register. However, if the first
byte still has not been read by the time reception of the second
byte is complete, the first byte is lost. The physical interface to
the serial data network is via Pins RxD (P3.0) and TxD (P3.1),
while the SFR interface to the UART is comprised of the
following registers.
Rev. A | Page 53 of 72
SBUF
The serial port receive and transmit registers are both accessed
through the SBUF SFR (SFR address = 99H). Writing to SBUF
loads the transmit register and reading SBUF accesses a
physically separate receive register.
SCON
SFR Address
Power-On Default
Bit Addressable
UART Serial Port Control Register
98H
00H
Yes
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Table 26. SCON SFR Bit Designations
Bit No.
Name
Description
7
SM0
6
SM1
These bits select the serial port operating mode as follows:
SM0
SM1
0
0
0
1
1
0
1
1
5
SM2
Multiprocessor Communication Enable Bit.
Enables multiprocessor communication in Modes 2 and 3.
In Mode 0, SM2 should be cleared.
In Mode 1, if SM2 is set, RI is not activated if a valid stop bit is not received. If SM2 is cleared, RI is set as soon as the byte
of data is received.
In Mode 2 or 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI is set as soon
as the byte of data is received.
4
REN
Serial Port Receive Enable Bit.
Set by the user software to enable serial port reception.
Cleared by the user software to disable serial port reception.
3
TB8
Serial Port Transmit (Bit 9).
The data loaded into TB8 is the ninth data bit that is transmitted in Modes 2 and 3.
2
RB8
Serial port Receiver Bit 9.
The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8.
1
TI
Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3.
Cleared by the user software.
0
RI
Serial Port Receive Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit in Modes 1, 2, and 3.
Cleared by user software.
UART Serial Mode Select Bits.
Selected Operating Mode
Mode 0: Shift Register, fixed baud rate (Core_Clk/2)
Mode 1: 8-bit UART, variable baud rate
Mode 2: 9-bit UART, fixed baud rate (Core_Clk/64) or (Core_Clk/32)
Mode 3: 9-bit UART, variable baud rate
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