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參數資料
| 型號： | ADUC848BS62-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 14 X 14 MM, PLASTIC, MO-112-AC-1, MQFP-52 |
| 文件頁數： | 35/108頁 |
| 文件大小： | 1109K |
| 代理商： | ADUC848BS62-5 |
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ADuC845/ADuC847/ADuC848
subtracts the offset calibration error, it is advisable to perform
an offset calibration at the same gain range as that used for full-
scale calibration. There is no penalty to the full-scale calibration
in redoing the zero-scale calibration at the required PGA range
because the full-scale calibration has very good matching at all
the PGA ranges.
Rev. A | Page 35 of 108
This procedure also applies when chop is disabled.
Note that for internal calibration to be effective, the AIN
pin
should be held at a steady voltage, within the allowable common-
mode range to keep it from floating during calibration.
System Calibration Example
With chop enabled, a system zero-scale or offset calibration
should never be required. However, if a full-scale or gain
calibration is required for any reason, use the following typical
procedure for doing so.
1.
Apply a differential voltage of 0 V to the selected analog
inputs (AIN+ to AIN) that are held at a common-mode
voltage.
Perform a system zero-scale or offset calibration by setting
the MD2...0 bits in the ADCMODE register to 110B.
2.
Apply a full-scale differential voltage across the ADC
inputs again at the same common-mode voltage.
Perform a system full-scale or gain calibration by setting
the MD2...0 bits in the ADCMODE register to 111B.
Perform a system calibration at the required PGA range to be
used since the ADC scales to the differential voltages that are
applied to the ADC during the calibration routines.
In bipolar mode, the zero-scale calibration determines the mid-
scale point of the ADC (800000H) or 0 V.
PROGRAMMABLE GAIN AMPLIFIER
The primary ADC incorporates an on-chip programmable gain
amplifier (PGA). The PGA can be programmed through eight
different ranges, which are programmed via the range bits (RN0
to RN2) in the ADC0CON1 register. With an external 2.5 V
reference applied, the unipolar ranges are 0 mV to 20 mV, 0 mV
to 40 mV, 0 mV to 80 mV, 0 mV to 160 mV, 0 mV to 320 mV,
0 mV to 640 mV, 0 V to 1.28 V and 0 V to 2.56 V, while in
bipolar mode the ranges are ±20 mV, ±40 mV, ±80 mV, ±160 mV,
±320 mV, ±64 0 mV, ±1.28 V, and ±2.56 V. These ranges should
appear on the input to the on-chip PGA. The ADC range-
matching specification of 2 μV (typical with chop enabled)
means that calibration need only be carried out on a single
range and need not be repeated when the ADC range is
changed. This is a significant advantage compared to similar
mixed-signal solutions available on the market. The auxiliary
(ADuC845 only) ADC does not incorporate a PGA, and the
gain is fixed at 0 V to 2.50 V in unipolar mode, and ±2.50 V in
bipolar mode.
BIPOLAR/UNIPOLAR CONFIGURATION
The analog inputs of the ADuC845/ADuC847/ADuC848 can
accept either unipolar or bipolar input voltage ranges. Bipolar
input ranges do not imply that the part can handle negative
voltages with respect to system AGND, but rather with respect
to the negative reference input. Unipolar and bipolar signals on
the AIN(+) input on the ADC are referenced to the voltage on
the respective AIN() input. AIN(+) and AIN() refer to the
signals seen by the ADC.
For example, if AIN() is biased to 2.5 V (tied to the external
reference voltage) and the ADC is configured for a unipolar
analog input range of 0 mV to > 20 mV, the input voltage range
on AIN(+) is 2.5 V to 2.52 V. On the other hand, if AIN(
)
is
biased to 2.5 V (again the external reference voltage) and the
ADC is configured for a bipolar analog input range of ±1.28 V,
the analog input range on the AIN(+) is 1.22 V to 3.78 V, that is,
2.5 V ± 1.28 V.
The modes of operation for the ADC are fully differential mode
or pseudo differential mode. In fully differential mode, AIN1 to
AIN2 are one differential pair, AIN3 to AIN4 are another pair
(AIN5 to AIN6, AIN7 to AIN8, and AIN9 to AIN10 are the
others). In differential mode, all AIN(
)
pin names imply the
negative analog input of the selected differential pair, that is,
AIN2, AIN4, AIN6, AIN8, AIN10. The term AIN(+) implies the
positive input of the selected differential pair, that is, AIN1,
AIN3, AIN5, AIN7, AIN9. In pseudo differential mode, each
analog input is paired with the AINCOM pin, which can be
biased up or tied to AGND. In this mode, the AIN(
)
implies
AINCOM and AIN(+) implies any one of the ten analog input
channels.
The configuration of the inputs (unipolar versus bipolar) is
shown in Figure 17.
AIN1
I
A
C
A
C
I
I
I
I
I
I
I
I
I
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AINCOM
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
FULLY DIFFERENTIAL
FULLY DIFFERENTIAL
FULLY DIFFERENTIAL
FULLY DIFFERENTIAL
FULLY DIFFERENTIAL
AINCOM
0
Figure 17. Unipolar and Bipolar Channel Pairs
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