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| 型號(hào)： | ADUC848BS62-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 14 X 14 MM, PLASTIC, MO-112-AC-1, MQFP-52 |
| 文件頁(yè)數(shù)： | 53/108頁(yè) |
| 文件大小： | 1109K |
| 代理商： | ADUC848BS62-5 |
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ADuC845/ADuC847/ADuC848
DAC CIRCUIT INFORMATION
The ADuC845/ADuC847/ADuC848 incorporate a 12-bit,
voltage output DAC on-chip. It has a rail-to-rail voltage output
buffer capable of driving 10 k/100 pF, and has two selectable
ranges, 0 V to V
REF
and 0 V to AV
DD
. It can operate in 12-bit or
8-bit mode. The DAC has a control register, DACCON, and two
data registers, DACH/L. The DAC output can be programmed
to appear at Pin 14 or Pin 13 (AINCOM).
DACCON Control Register
SFR Address:
FDH
Power-On Default:
00H
Bit Addressable:
No
Rev. A | Page 53 of 108
Note that in 12-bit mode, the DAC voltage output is updated as
soon as the DACL data SFR is written; therefore, the DAC data
registers should be updated as DACH first, followed by DACL.
The 12-bit DAC data should be written into DACH/L right-
justified such that DACL contains the lower 8 bits, and the
lower nibble of DACH contains the upper 4 bits.
Table 33. DACCON—DAC Configuration Commands
Bit No.
Name
Description
7
–––
Not Implemented. Write Don’t Care.
6
–––
Not Implemented. Write Don’t Care.
5
–––
Not Implemented. Write Don’t Care.
4
DACPIN
DAC Output Pin Select.
Set to 1 by the user to direct the DAC output to Pin 13 (AINCOM).
Cleared to 0 by the user to direct the DAC output to Pin 14 (DAC).
3
DAC8
DAC 8-Bit Mode Bit.
Set to 1 by the user to enable 8-bit DAC operation. In this mode, the 8 bits in DACL SFR are routed to the 8 MSBs
of the DAC, and the 4 LSBs of the DAC are set to 0.
Cleared to 0 by the user to enable 12-bit DAC operation. In this mode, the 8 LSBs of the result are routed to
DACL, and the upper 4 MSB bits are routed to the lower 4 bits of DACH.
2
DACRN
DAC Output Range Bit.
Set to 1 by the user to configure the DAC range of 0 V to AV
DD
.
Cleared to 0 by the user to configure the DAC range of 0 V to 2.5 V (V
REF
).
1
DACCLR
DAC Clear Bit.
Set to 1 by the user to enable normal DAC operation.
Cleared to 0 by the user to reset the DAC data registers DACL/H to 0.
0
DACEN
DAC Enable Bit.
Set to 1 by the user to enable normal DAC operation.
Cleared to 0 by the user to power down the DAC.
DACH/DACL Data Registers
These DAC data registers are written to by the user to update
the DAC output.
S
FR Address:
DACH (DAC Data High Byte)—FCH
Power-On Default:
00H (Both Registers)
Bit Addressable:
No (Both Registers)
DACL (DAC Data Low Byte)—FBH
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參數(shù)描述 |
|---|---|
| ADUC848BS8-3 | 制造商:Analog Devices 功能描述: |
| ADUC848BS8-5 | 制造商:Analog Devices 功能描述:MCU 8-bit ADuC8xx 8052 CISC 62KB Flash 3.3V/5V 52-Pin MQFP 制造商:Analog Devices 功能描述:IC MICROCONTROLLER |
| ADUC848BSZ32-3 | 功能描述:IC MCU FLASH W/16BIT ADC 52MQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標(biāo)準(zhǔn)包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲(chǔ)器容量:4KB（4K x 8） 程序存儲(chǔ)器類(lèi)型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱(chēng):269-4116Z8F0413SH005EG-ND |
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| ADUC848BSZ62-3 | 功能描述:IC MCU FLASH W/16BIT ADC 52MQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標(biāo)準(zhǔn)包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲(chǔ)器容量:4KB（4K x 8） 程序存儲(chǔ)器類(lèi)型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱(chēng):269-4116Z8F0413SH005EG-ND |
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