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參數(shù)資料
| 型號： | ADUM3100BRZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Digital Isolator, Enhanced System-Level ESD Reliability |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | ROHS COMPLIANT, MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 289K |
| 代理商： | ADUM3100BRZ |
ADuM3100
Parameter
Change vs. Temperature
7
5 V/3 V Operation
3 V/5 V Operation
Propagation Delay Skew (Equal Temperature)
6, 8
5 V/3 V Operation
3 V/5 V Operation
Propagation Delay Skew (Equal Temperature,
Supplies)
6, 8
5 V/3 V Operation
3 V/5 V Operation
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at
Logic Low/High Output
9
Input Dynamic Supply Current per Channel
10
5 V/3 V Operation
3 V/5 V Operation
Output Dynamic Supply Current per Channel
10
5 V/3 V Operation
3 V/5 V Operation
1
All voltages are relative to their respective ground.
2
Output supply current values are with no output load present. See Figure 4 and Figure 5 for information on supply current variation with logic signal frequency. See
the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.
3
The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
5
t
PHL
is measured from the 50% level of the falling edge of the V
I
signal to the 50% level of the falling edge of the V
O
signal. t
PLH
is measured from the 50% level of the
rising edge of the V
I
signal to the 50% level of the rising edge of the V
O
signal.
6
Because the input thresholds of the ADuM3100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse-width
distortion can be affected by slow input rise/fall times. See the System-Level ESD Considerations and Enhancements section and Figure 13 to Figure 17 for information
on the impact of given input rise/fall times on these parameters.
7
Pulse-width distortion change vs. temperature is the absolute value of the change in pulse-width distortion for a 1°C change in operating temperature.
8
t
PSK1
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating temperature and output load within the
recommended operating conditions. t
PSK2
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating
temperature, supply voltages, and output load within the recommended operating conditions.
9
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range
over which the common-mode is slewed.
10
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 4 and Figure 5 for information on
supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given
data rate and output load.
Rev. A | Page 6 of 16
Symbol
t
PSK1
t
PSK2
Min
Typ
3
10
Max
12
15
Unit
ps/oC
ps/oC
ns
ns
Test Conditions
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
t
R
, t
f
|CM
L
|, |CM
H
|
25
3
35
9
12
ns
ns
ns
kV/μs
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
V
I
= 0 or V
DD1
, V
CM
= 1000 V,
transient magnitude = 800 V
I
DDI (D)
I
DDO (D)
0.09
0.08
0.01
0.02
mA/Mbps
mA/Mbps
mA/Mbps
mA/Mbps
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