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參數資料
| 型號： | ADV3000-EVALZ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 3:1 HDMI/DVI Switch with Equalization |
| 中文描述： | 3:1的HDMI / DVI接口與均衡開關 |
| 文件頁數： | 17/28頁 |
| 文件大小： | 608K |
| 代理商： | ADV3000-EVALZ |
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ADV3000
SERIAL INTERFACE CONFIGURATION REGISTERS
The serial interface configuration registers can be read and written using the I
2
C serial control interface, Pin I2C_SDA, and Pin I2C_SCL.
The least significant bit of the ADV3000 I
2
C part address is set by tying Pin I2C_ADDR0 to 3.3 V (Logic 1) or 0 V (Logic 0). As soon
as
the serial control interface is used, the parallel control interface is disabled until the ADV3000 is reset as described in the Serial Control
Interface section.
Rev. 0 | Page 17 of 28
Table 5. Serial (I
2
C) Interface Register Map
Name
Bit 7
High Speed
Device
Modes
Bit 6
High
speed
switch
enable
HS_EN
Auxiliary
switch
enable
AUX_EN
Bit 5
High speed switching
mode select
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr.
0x00
Default
0x40
High speed source select
0
0
0
0
HS_CH[1]
Auxiliary switch source select
HS_CH[0]
Auxiliary
Device
Modes
0
0
0
0
AUX_CH[1]
AUX_CH[0]
High speed input
termination select
RX_TO
0x01
0x40
Receiver
Settings
0x10
0x01
Source A and Source B : input termination pulse-on-source switch select
(disconnect termination for a short period of time)
RX_PT[6]
RX_PT[5]
RX_PT[4]
RX_PT[3]
Source C: input termination pulse-on-source switch select
(disconnect termination for a short period of time)
0
0
0
RX_PT[11]
Source A and Source B: input equalization level select
RX_EQ[6]
RX_EQ[5]
RX_EQ[4]
RX_EQ[3]
Source C input equalization level select
0
0
0
RX_EQ[11]
High speed output
pre-emphasis level
Input
Termination
Pulse 1
RX_PT[7]
RX_PT[2]
RX_PT[1]
RX_PT [0]
0x11
0x00
Input
Termination
Pulse 2
0
RX_PT[10]
RX_PT[9]
RX_PT[8]
0x12
0x00
Receive
Equalizer 1
RX_EQ[7]
RX_EQ[2]
RX_EQ[1]
RX_EQ[0]
0x13
0x00
Receive
Equalizer 2
0
RX_EQ[10]
RX_EQ[9]
High speed
output
termination
select
TX_PTO
RX_EQ[8]
High speed output
current level select
0x14
0x00
select
Transmitter
Settings
TX_PE[1]
TX_PE[0]
TX_OCL
0x20
0x03
HIGH SPEED DEVICE MODES REGISTER
HS_EN: High Speed (TMDS) Channels Enable Bit
Table 6. HS_EN Description
HS_EN
Description
0
High speed channels off, low power/standby mode
1
High speed channels on
HS_CH[1:0]: High Speed (TMDS) Switch Source Select Bus
Table 7. HS_EN Mapping
HS_CH[1:0]
00
01
10
11
O[3:0]
A[3:0]
B[3:0]
C[3:0]
Description
High Speed Source A switched to output
High Speed Source B switched to output
High Speed Source C switched to output
Illegal value
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