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參數資料
| 型號： | ADV7125KST50 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | CMOS, 330 MHz Triple 8-Bit High Speed Video DAC |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PQFP48 |
| 封裝： | 1.40 MM, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數： | 12/12頁 |
| 文件大小： | 264K |
| 代理商： | ADV7125KST50 |
REV. 0
C
P
–12–
ADV7125
Analog Signal Interconnect
The ADV7125 should be located as close as possible to the
output connectors, thus minimizing noise pickup and reflections
due to impedance mismatch.
The video output signals should overlay the ground plane and
not the analog power plane, thereby maximizing the high fre-
quency power supply rejection.
For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75
(doubly termi-
nated 75
configuration). This termination resistance should
be as close as possible to the ADV7125 to minimize reflections.
Additional information on PCB design is available in an application
note entitled
Design and Layout of a Video Graphics System for
Reduced EMI
. This application note is available from Analog
Devices, publication no. E1309–15–10/89 (www.analog.com/
library/applicationNotes/designTech/AN333.pdf).
OUTLINE DIMENSIONS
48-Lead Plastic Quad Flatpack [LQFP]
1.4 mm Thick
(ST-48)
Dimensions shown in millimeters
TOP VIEW
(PINS DOWN)
1
12
13
25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
7.00
BSC
SEATING
PLANE
1.60 MAX
0.75
0.60
0.45
VIEW A
7
3.5
0
0.20
0.09
1.45
1.40
1.35
0.15
0.05
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90 CCW
PIN 1
INDICATOR
9.00 BSC
COMPLIANT TO JEDEC STANDARDS MS-026BBC
SEATING
PLANE
GND
R
SET
IOR
IOG
IOB
ADV7125
75
COMP
COMPLEMENTARY
OUTPUTS
R7–R0
G7–G0
B7–B0
CLOCK
VIDEO
DATA
INPUTS
ANALOG GROUND PLANE
L1
(FERRITE BEAD)
V
AA
V
REF
R
SET
530
IOR
IOG
IOB
75
75
75
75
0.1 F
0.1 F
10 F
0.01 F
33 F
0.1 F
5V (V
AA
)
POWER SUPPLY DECOUPLING (0.1 F AND 0.01 F
CAPACITOR FOR EACH V
AA
GROUP)
COAXIAL CABLE
75
13, 29,
30
1, 2, 14, 15,
25, 26, 39, 40
41–48
3–10
16–23
MONITOR
(CRT)
BNC
CONNECTORS
5V (V
AA
)
V
CC
V
AA
SYNC
BLANK
PSAVE
75
Figure 7. Typical Connection Diagram
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