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參數資料
| 型號： | ADV7125KST50 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | CMOS, 330 MHz Triple 8-Bit High Speed Video DAC |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PQFP48 |
| 封裝： | 1.40 MM, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數： | 7/12頁 |
| 文件大小： | 264K |
| 代理商： | ADV7125KST50 |
REV. 0
ADV7125
–7–
PIN FUNCTION DESCRIPTIONS
Pin Number
Mnemonic
Function
1, 2, 14, 15, 25,
26, 39, 40
3–10,
16–23,
41–48
11
GND
Ground. All GND pins must be connected.
G0–G7,
B0–B7,
R0–R7
BLANK
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge
of CLOCK. R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should
be connected to either the regular PCB power or ground plane.
Composite Blank Control Input (TTL Compatible). A logic zero on this control input drives the
analog outputs, IOR, IOB, and IOG, to the blanking level. The
BLANK
signal is latched on the
rising edge of CLOCK. While
BLANK
is a logical zero, the R0–R7, G0–G7, and B0–B7 pixel
inputs are ignored.
Composite Sync Control Input (TTL Compatible). A logical zero on the
SYNC
input switches
off a 40 IRE current source. This is internally connected to the IOG analog output.
SYNC
does
not override any other control or data input; therefore, it should only be asserted during the
blanking interval.
SYNC
is latched on the rising edge of CLOCK. If sync information is not
required on the green channel, the
SYNC
input should be tied to logical zero.
Analog Power Supply (5 V
±
5%). All V
AA
pins on the ADV7125 must be connected.
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7,
SYNC
, and
BLANK
pixel and control inputs. It is typically the pixel clock rate of the video
system. CLOCK should be driven by a dedicated TTL buffer.
Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These
RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly
terminated 75
load. If the complementary outputs are not required, these outputs should be
tied to ground.
Red, Green, and Blue Current Outputs. These high impedance current sources are capable of
directly driving a doubly terminated 75
coaxial cable. All three current outputs should have
similar output loads whether or not they are all being used.
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1
μ
F
ceramic capacitor must be connected between COMP and V
AA
.
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V)
A resistor (R
SET
) connected between this pin and GND controls the magnitude of the full-scale
video signal. Note that the IRE relationships are maintained, regardless of the full-scale output
current. The relationship between R
SET
and the full-scale output current on IOG (assuming I
SYNC
is connected to IOG) is given by:
R
The relationship between R
SET
and the full-scale output current on IOR, IOG, and IOB is given by:
IOG mA
IOR IOB mA
12
SYNC
13, 29, 30
24
V
AA
CLOCK
27, 31, 33
IOR
,
IOG
,
IOB
28, 32, 34
IOR, IOG, IOB
35
COMP
36
37
V
REF
R
SET
V
V
( )
IOG mA
SET
REF
( )
=
×
)
11 445
,
/
The equation for IOG will be the same as that for IOR and IOB when
SYNC
is not being used,
i.e.,
SYNC
tied permanently low.
Power Save Control Pin. Reduced power consumption is available on the ADV7125 when this
pin is active.
38
PSAVE
V
V
( )
V
REF
R
( )
SYNC being asserted
( )(
R
SET
/
( )
REF
.
SET
V
,
)
=
×
)
11 444 8
,
)
=
.
/
,
×
7 989 6
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