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| 型號： | ADV7127KR50 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | CMOS, 240 MHz 10-Bit High Speed Video DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 307K |
| 代理商： | ADV7127KR50 |
–6–
REV. 0
ADV7127–SPECIFICATIONS
5 V/3.3 V DYNAMIC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
DAC PERFORMANCE
Glitch Impulse
2, 3
Data Feedthrough
2, 3
Clock Feedthrough
2, 3
10
22
33
pVs
dB
dB
NOTES
1
These max/min specifications are guaranteed by characterization.
2
TTL input values are for 0 V and 3 V with input rise/fall times
≤
3 ns, measured at the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
3
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
Specifications subject to change without notice.
(V
AA
= (3 V–5.25 V)
1
, V
REF
= 1.235 V, R
SET
= 560
V
, C
L
= 10 pF. All specifications
are for T
A
= +25
8
C unless otherwise noted, T
J
MAX
= 110
8
C)
5 V TIMING SPECIFICATIONS
1
Parameter
Min
Typ
Max
Units
Condition
ANALOG OUTPUTS
Analog Output Delay, t
6
Analog Output Rise/Fall Time, t
74
Analog Output Transition Time, t
85
Analog Output Skew, t
96
5.5
1.0
15
1
ns
ns
ns
ns
2
CLOCK CONTROL
f
CLK7
f
CLK7
f
CLK7
Data and Control Setup, t
1
Data and Control Hold, t
2
Clock Pulsewidth High, t
4
Clock Pulsewidth Low t
5
Clock Pulsewidth High t
4
Clock Pulsewidth Low t
5
Clock Pulsewidth High t
4
Clock Pulsewidth Low t
5
Pipeline Delay, t
PD6
PSAVE Up Time, t
106
PDOWN Up Time, t
118
0.5
0.5
0.5
1.5
2.5
1.875
1.875
2.85
2.85
8.0
8.0
1.0
50
140
240
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
ns
ns
50 MHz Grade
140 MHz Grade
240 MHz Grade
1.1
1.25
f
MAX
= 240 MHz
f
MAX
= 240 MHz
f
MAX
= 140 MHz
f
MAX
= 140 MHz
f
MAX
= 50 MHz
f
MAX
= 50 MHz
1.0
2
320
1.0
10
NOTES
1
Timing specifications are measured with input levels of 3.0 V (V
) and 0 V (V
IL
) 0 for both 5 V and 3.3 V supplies.
2
These maximum and minimum specifications are guaranteed over this range.
3
Temperature range: T
to T
: –40
°
C to +85
°
C at 50 MHz and 140 MHz, 0
°
C to +70
°
C at 240 MHz.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
max specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
8
This power-down feature is only available on the ADV7127 in the TSSOP package.
Specifications subject to change without notice.
(V
AA
= +5 V
6
5%
2
, V
REF
= 1.235 V, R
SET
= 560
V
, C
L
= 10 pF. All specifications T
MIN
to T
MAX3
unless otherwise noted, T
J
MAX
= 110
8
C)
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