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參數資料
| 型號： | ADV7152LS110 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| 中文描述： | PALETTE-DAC DSPL CTLR, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 18/32頁 |
| 文件大小： | 454K |
| 代理商： | ADV7152LS110 |
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ADV7152
–18–
REV. B
RE GIST E R PROGRAMMING
T he following section describes each register, including Address
Register, Mode Register and each of the nine Control Registers
in terms of its configuration.
Address Register (A7–A0)
As illustrated in the previous tables, the C0 and C1 control in-
puts, in conjunction with this address register specify which con-
trol register, or color palette location is accessed by the MPU
port. T he address register is 8-bits wide and can be read from as
well as written to. When writing to or reading from the color
palette on a sequential basis, only the start address needs to be
written. After a red, green and blue write sequence, the address
register is automatically incremented.
MODE RE GIST E R MR1 (MR19–MR10)
T he mode register is a 10-bit wide register. However for pro-
gramming purposes, it may be considered as an 8-bit wide regis-
ter (MR18 and MR19 are both reserved). It is denoted as
MR17–MR10 for simplification purposes.
T he diagram shows the various operations under the control of
the mode register. T his register can be read from as well written
to. In read mode, if MR18 and MR19 are read back, they are
both returned as zeros.
MODE RE GIST E R (MR17–MR10) BIT DE SCRIPT ION
Reset Control (MR10)
T his bit is used to reset the pixel port sampling sequence. T his
ensures that the pixel sequence AB starts at A. It is reset by writ-
ing a “1” followed by a “0” followed by a “1.” T his bit must be
run through this cycle during the initialization sequence.
RAM-DAC Resolution Control (MR11)
When this is programmed with a “1,” the RAM is 30 bits deep
(10 bits each for red, green and blue) and each of the three
DACs is configured for 10-bit resolution. When MR11 is pro-
grammed with a “0,” the RAM is 24 bits deep (8 bits each for
red, green and blue) and the DACs are configured for 8-bit
resolution. T he two LSBs of the 10-bit DACs are pulled down
to zero in 8-bit RAM-DAC mode.
MPU Databus Width (MR12)
T his bit determines the width of the MPU port. It is configured
as either a 10-bit wide (D9–D0) or 8-bit wide (D7–D0) bus.
10-bit data can be written to the device when configured in
8-bit wide mode. T he 8 MSBs are first written on D7–D0, then
the two LSBs are written over D1–D0. Bits D9–D8 are zeros in
8-bit mode.
Operational Mode Control (MR14–MR13)
When MR14 is “0” and MR13 is “1,” the part operates in
normal mode.
Calibrate LOADIN (MR15)
T his bit automatically calibrates the onboard L OADIN/
LOADOUT synchronization circuit. A “0” to “1” transition
initiates calibration. T his bit is set to “0” in normal operation.
See “Pipeline Delay and Calibration” section. T his bit must be
run through this cycle during the initialization sequence.
Palette Select Match Bits Control (MR17–MR16)
T hese bits allow multiple palette devices to work together.
When bits PSI and PS0 match MR17 and MR16 respectively,
the device is selected. If these bits do not match, the device is
not selected and the analog video outputs drive 0 mA, see
“Palette Priority Select Inputs” section.
Control Registers
T he ADV7152 has 9 control registers. T o access each register,
two write operations must be performed. T he first write to the
address register specifies which of the 9 registers is to be ac-
cessed. T he second access determines the value written to that
particular control register.
Pixel T est Register
(Address Reg (A7–A0) = 00H )
T his register is used when the device is in test/diagnostic mode.
It is a 24-bit (8 bits each for RED, GREEN and BLUE) wide
read-only register which allows the MPU to read data on the
pixel port, see “T est Diagnostic” section.
MR17
MR16
MR14
MR13
MR12
MR11
MR10
MR15
MR19
MR18
CALIBRATE
LOADIN
MR15
*
THESE BITS ARE READ-ONLY RESERVED BITS.
A READ CYCLE WILL RETURN ZEROS "00."
RESERVED*
RAM-DAC
RESOLUTION CONTROL
MR11
0 8-BIT
1 10-BIT
RESET CONTROL
MR10
MR16 PS0
MR17 PS1
PALETTE SELECT
MATCH BITS CONTROL
MPU DATA BUS
WIDTH
MR12
0 8-BIT (D7–D0)
1 10-BIT (D9–D0)
OPERATIONAL MODE CONTROL
0 0 RESERVED
0 1 NORMAL OPERATION
1 0 RESERVED
1 1 RESERVED
MR14 MR13
Mode Register 1 (MR1) (MR19–MR10)
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|---|---|
| ADV7152LS135 | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| ADV7152LS170 | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| ADV7152LS220 | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| ADV7160 | 96-Bit, 220 MHz True-Color Video RAM-DAC(96位,220MHz,真彩色視頻RAM-D/A轉換器) |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7152LS135 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADV7152LS170 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| ADV7152LS220 | 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:PALETTE-DAC DSPL CTLR, PQFP100 |
| ADV7152LS85 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| ADV7160 | 制造商:AD 制造商全稱:Analog Devices 功能描述:96-Bit, 220 MHz True-Color Video RAM-DAC |
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