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參數(shù)資料
| 型號(hào)： | ADV7152LS85 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| 中文描述： | PALETTE-DAC DSPL CTLR, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 12/32頁(yè) |
| 文件大小： | 454K |
| 代理商： | ADV7152LS85 |
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ADV7152
–12–
REV. B
Alternatively, the ADV7152 CLOCK inputs can be driven by a
Programmable Clock Generator (Figure 13), such as the
ICS1562. T he ICS1562 is a monolithic, phase-locked-loop,
clock generator chip. It is capable of synthesizing differential
ECL output frequencies in a range up to 220 MHz from a single
low frequency reference crystal.
V
CC
GND
220
330
GND
+5V
CLOCK
CLOCK
GND
V
AA
ADV7152
GND
D0–D3
CS R/W
ECL
OUT+
V
REF
OUT
V
REF
+5V
V
CLOCK
V
AA
0.1
μ
F
LOW FREQUENCY
OSCILLATOR
V
CC
GND
220
330
ECL
OUT–
CLOCK
GENERATOR
Figure 13. PLL Generator Driving CLOCK,
CLOCK
of the
ADV7152
CLOCK CONT ROL SIGNALS LOADOUT
T he ADV7152 generates a LOADOUT control signal which
runs at a divided down frequency of the pixel CLOCK . T he
frequency is automatically set to the programmed multiplex
rate, controlled by CR36 of Command Register 3.
f
LOADOUT
= f
CLOCK
/2
2:1 Multiplex Mode
f
LOADOUT
= f
CLOCK
1:1 Multiplex Mode
T he LOADOUT signal is used to directly drive the LOADIN
pixel latch signal of the ADV7152. T his is most simply achieved
by tying the LOADOUT and LOADIN pins together. Alterna-
tively, the LOADOUT signal can be used to drive the frame
buffer’s shift clock signals, returning to the LOADIN input de-
layed with respect to LOADOUT .
LOADOUT
LOADIN
ADV7152
VIDEO
FRAME
BUFFER
LOADOUT
LOADIN
ADV7152
VIDEO
FRAME
BUFFER
LOADOUT(1)
LOADOUT(2)
PIXEL
DATA
PIXEL
DATA
LOADOUT(1)
LOADIN
LOADOUT(2)
LOADOUT
DELAY
Figure 14. LOADOUT vs. Pixel Clock Input (CLOCK,
CLOCK
)
If it is not necessary to have a known fixed number of pipeline
delays, then there is no limitation on the delay between LOAD-
OUT and LOADIN (LOADOUT (1) and LOADOUT (2)).
LOADIN and Pixel Data must conform to the setup and hold
times (t
8
and t
9
).
If however, it is required that the ADV7152 has a fixed number
of pipeline delays (t
PD
), LOADOUT and LOADIN must con-
form to timing specifications t
10
and
τ
-t
11
as illustrated in Fig-
ures 4 and 5.
PRGC K OUT
T he PRGCK OUT control signal outputs a user programmable
clock frequency. It is a divided down frequency of the pixel
CLOCK (see Figure 8). T he rising edge of PRGCK OUT is
synchronous to the rising edge of LOADOUT
f
PRGCKOUT
= f
CLOCK
/N
where
N
= 4, 8, 16 or 32.
One application of the PRGCK OUT is to use it as the master
clock frequency of the graphics subsystems processor or
controller.
SCK IN, SCK OUT
T hese video memory signals are used to minimize external sup-
port chips. Figure 15 illustrates the function that is provided.
An input signal applied to SCK IN is synchronously AND-ed
with the video blanking signal (
BLANK
). T he resulting signal is
output on SCK OUT . Figure 7 of the T iming Waveform section
shows the relationship between SCK OUT , SCK IN and
BLANK
.
SCKOUT
SCKIN
BLANK
LATCH
ENABLE
SYNC
Figure 15. SCKOUT Generation Circuit
T he SCK OUT signal is essentially the video memory shift con-
trol signal. It is stopped during the screen retrace. Figure 16
shows a suggested frame buffer to ADV7152 interface. T his is a
minimum chip solution and allows the ADV7152 control the
overall graphics system clocking and synchronization.
LOADOUT
SCKOUT
ADV7152
VIDEO
FRAME
BUFFER
PIXEL
DATA
LOADIN
SCKIN
BLANK
Figure 16. ADV7152 Interface Using SCKIN and SCKOUT
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| ADV7152LS110 | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
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|---|---|
| ADV7160 | 制造商:AD 制造商全稱:Analog Devices 功能描述:96-Bit, 220 MHz True-Color Video RAM-DAC |
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| ADV7160KS220 | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| ADV7162 | 制造商:AD 制造商全稱:Analog Devices 功能描述:96-Bit, 220 MHz True-Color Video RAM-DAC |
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