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參數資料
| 型號： | ADV7152LS85 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| 中文描述： | PALETTE-DAC DSPL CTLR, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 16/32頁 |
| 文件大?。?/td> | 454K |
| 代理商： | ADV7152LS85 |
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ADV7152
–16–
REV. B
Data is read from the color palette by first writing to the address
register of the color palette location to be read. T he MPU per-
forms three successive read cycles from each of the red, green
and blue locations (10-bit or 8-bit) of the RAM. An internal
pointer moves from red to green to blue after each read is com-
pleted. T his pointer is reset to red after a blue read or whenever
the address register is written. T he address register then auto-
matically increments to point to the next RAM location, and a
similar red, green and blue palette read sequence is performed.
T he address register resets to 00H following a blue read cycle of
color palette RAM location FFH.
Register Accesses
T he MPU can write to or read from all of the ADV7152s regis-
ters. C0 and C1 determine whether the Mode Register or Ad-
dress Register is being accessed. Access to these registers is
direct. T he Control Registers are accessed indirectly. T he
Address Register must point to the desired Control Register.
Figure 28 along with the 8-bit and 10-bit Interface T ruth T ables
illustrate the structure and protocol for device communication
over the MPU port.
T able III. Interface T ruth T able (10-Bit Databus Mode)
R/
W
C1
C0
Databus (D9–D0)
Operation
Result
0
0
0
1
0
1
1
0
0
DB7–DB0
DB7–DB0
DB7–DB0
Write to Mode Register
Write to Address Register
Write to Control Registers
(
Particular Control Register Determined by Address Register
)
DB7–DB0
MR17–MR10
DB7–DB0
A7–A0
DB7–DB0
Control Register
0
0
0
0
0
0
1
1
1
DB9–DB0
DB9–DB0
DB9–DB0
Write to RED Register
Write to GREEN Register
Write to BLUE Register
Write RGB Data to RAM Location Pointed to by Address Register (A7–A0)
Address Register = Address Register + 1
DB9–DB0
R9–R0
DB9–DB0
G9–G0
DB9–DB0
B9–B0
1
1
1
1
0
1
1
0
0
DB7–DB0
DB7–DB0
DB7–DB0
Read Mode Register
Read Address Register
Read Control Registers
(Particular Control Register Determined by Address Register)
MR17–MR10
DB7–DB0
A7–A0
DB7–DB0
Register Data
DB7–DB0
1
1
1
0
0
0
1
1
1
DB9–DB0
DB9–DB0
DB9–DB0
Read RED RAM Location
Read GREEN RAM Location
Read BLUE RAM Location
(RAM Location Pointed to by Address Reg (A7–A0))
Address Register = Address Register + 1
R9–R0
DB9–DB0
G9–G0
DB9–DB0
B9–B0
DB9–DB0
DB = Data Bit.
ADDRESS REG =
ADDRESS REG + 1
MODE REGISTER
(MR17–MR10)
ADDRESS REGISTER
(A7–A0)
CONTROL
REGISTERS
PIXEL TEST REGISTER
R G B
COMMAND REGISTER 2
*
THIS REGISTER IS READ ONLY.
LOOK-UP TABLE RAM
(256 x 30)
RED
REGISTER
(R9–R0)
POINTS TO LOCATION
CORRESPONDING TO
ADDRESS REG (A7–A0)
C1 = 0
C0 = 1
C1 = 1
C0 = 1
C1 = 0
C0 = 0
DAC TEST REGISTER
R G B
SYNC, BLANK & I
PLL
TEST REGISTER
C1 = 1
C0 = 0
ID REGISTER (READ ONLY)
PIXEL MASK REGISTER
COMMAND REGISTER 1
COMMAND REGISTER 3
RESERVED
*
(READ ONLY)
RESERVED
*
(READ ONLY)
RESERVED
*
(READ ONLY)
REVISION REGISTER
ADDRESS
REGISTER
(A7–A0)
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
00H
01H
02H
GREEN
REGISTER
(G9–G0)
BLUE
REGISTER
(B9–B0)
Figure 26. Internal Register Configuration and Address Decoding
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