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參數資料
| 型號： | ADV7162KS220 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | 96-Bit, 220 MHz True-Color Video RAM-DAC |
| 中文描述： | 1600 X 1200 PIXELS PALETTE-DAC DSPL CTLR, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數： | 13/44頁 |
| 文件大小： | 668K |
| 代理商： | ADV7162KS220 |
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ADV7160/ADV7162
REV. 0
–13–
PIN FUNCTION DESCRIPTION
Mnemonic
Function
RED (R0
A
. . . R0
B
– R7
A
. . . R7
D
), GREEN (G0
A
. . . G0
D
– G7
A
. . . G7
D
), BLUE (B0
A
. . . B0
D
– B7
A
. . . B7
D
):
Pixel Port (TTL Compatible Inputs): 96 pixel select inputs, with 8 bits each for Red, Green and Blue.
Each bit is multiplexed [A-D] 4:1 or 2:1. It can be configured for 24-Bit True-Color Data, 8-Bit
Pseudo-Color Data, 16-Bit True-Color and 15-Bit True-Color Data formats. In 8-Bit Pseudo-Color
Mode, there is a special case whereby 8:1 multiplexing is also available. It will be explained in more
detail later. Pixel Data is latched into the device on the rising edge of LOADIN.
PS0
A
. . . PS0
D
, PS1
A
. . . PS1
D
Palette Priority Selects (TTL Compatible Inputs): The eight PS inputs provide two Bits after input
multiplexing. These pixel port select inputs can be configured for three separate functions. In Overlay
Mode, these inputs provide a three color overlay function. With any value other than “00” on the
overlay inputs, the color displayed comes from the overlay palette instead of the main pixel inputs.
For the ADV7160, in Bypass Mode, PS1 specifies for each pixel whether it should pass through the
Color Matrix and Color Palette or bypass the Matrix and Palette. PS0 acts as an overlay input. (This
mode is not available for the ADV7162.) Palette Select Mode is used to multiplex the RGB outputs of
a number of devices. When the palette mode inputs match the PS bits in the mode register, the part
operates as normal. When there is a mismatch, the RGB outputs are switched to zero, allowing the
RGB outputs of another device to drive the monitor.
LOADIN
Pixel Data Load Input (TTL Compatible Input): This input latches the multiplexed pixel data, in-
cluding PS0-PS1,
BLANK
,
TRISYNC
,
SYNC
and ODD/
EVEN
into the device.
LOADOUT
Pixel Data Load Output (TTL Compatible Output): This output control signal runs at a divided
down frequency of the pixel clock. Its frequency is a function of the multiplex rate. It can be used to
directly or indirectly drive LOADIN.
f
LOADOUT
= f
CLOCK
/M
where
(M = 2 for 2:1 Multiplex Mode)
(M = 4 for 4:1 Multiplex Mode)
(M = 8 for 8:1 Multiplex Mode)
PRGCKOUT
Programmable Clock Output (TTL Compatible Output): This output control signal runs at a divided
down frequency of the pixel Clock. Its frequency is user programmable and is determined by bits
CR30 and CR31 of Command Register 3.
f
PRGCKOUT
= f
CLOCK
/N
where N = 4, 8, 16 & 32
SCKIN
Video Shift Clock Input (TTL Compatible Input): The signal on this input is internally gated syn-
chronously with the
BLANK
signal. The resultant output, SCKOUT, is a video clocking signal that
is stopped during video blanking periods. It is normally driven by a divided down version of the
CLOCK frequency.
SCKOUT
Video Shift Clock Output (TTL Compatible Output): This output is a synchronously gated version of
SCKIN and
BLANK
. SCKOUT is a video clocking signal that is stopped during video blanking
periods.
CLOCK,
CLOCK
Clock Inputs (ECL Compatible Inputs): These differential clock inputs are designed to be driven by
ECL logic levels configured for single supply (+5 V) operation. The clock rate is normally the pixel
clock rate of the system.
PLL
REF
PLL Clock Input (TTL Compatible Input): This clock input is designed to be driven by TTL logic
levels. The PLL is then configured to output a specific frequency depending on the PLL Registers.
See PLL section for more detail.
BLANK
Composite Blank (TTL Compatible Input): This video control signal drives the analog outputs to the
blanking level.
SYNC
Composite-Sync Input (TTL Compatible Input): This video control signal drives any of the analog
outputs to the
SYNC
level. It is only asserted during the blanking period. CR22 in Command
Register 2 must be set if
SYNC
is to be decoded onto the IOG analog output, CR41 in Command
Register 4 must be set if
SYNC
is to be decoded onto the IOR analog output, CR42 in Command
Register 4 must be set if
SYNC
is to be decoded onto the IOB analog output, otherwise the
SYNC
input is ignored.
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