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參數(shù)資料
| 型號： | ADV7170 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power Management |
| 中文描述： | 數(shù)碼PAL / NTSC視頻編碼器與10位SSAF⑩和高級電源管理 |
| 文件頁數(shù)： | 35/55頁 |
| 文件大?。?/td> | 754K |
| 代理商： | ADV7170 |
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ADV7170/ADV7171
–35–
REV. 0
APPENDIX 5
TELETEXT INSERTION
t
PD
is the time needed by the ADV7170/ADV7171 to interpolate input data on TTX and insert it onto the CVBS or Y outputs, such
that it appears t
SYNTXTOUT
= 10.2
μ
s after the leading edge of the horizontal signal. Time TXT
DEL
is the pipeline delay time by the
source that is gated by the TTREQ signal in order to deliver TTX data.
With the programmability offered with TTXREQ signal on the Rising/Falling edges, the TTX data is always inserted at the correct
position of 10.2
μ
s after the leading edge of Horizontal Sync pulse, thus enabling a source interface with variable pipeline delays.
The width of the TTXREQ signal must always be maintained to allow the insertion of 360 (to comply with the Teletext Standard
“PAL-WST”) teletext bits at a text data rate of 6.9375 Mbits/s, this is achieved by setting TC03–TC00 to zero. The insertion win-
dow is not open if the Teletex Enable bit (MR34) is set to zero.
Teletext Protocol
The relationship between the TTX bit clock (6.9375 MHz) and the system CLOCK (27 MHz) for 50 Hz is given as follows:
(27 MHz/4) = 6.75 MHz
(6.9375
×
10
6
/6.75
×
10
6
) = 1.027777
Thus 37 TTX bits correspond to 144 clocks (27 MHz) and each bit has a width of almost four clock cycles. The ADV7170/ADV7171
uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal
that can be outputted on the CVBS and Y outputs.
At the TTX input the bit duration scheme repeats after every 37 TTX bits or 144 clock cycles. The protocol requires that TTX Bits
10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. After 37 TTX bits, the next bits with three clock
cycles are 47, 56, 65 and 74. This scheme holds for all following cycles of 37 TTX bits, until all 360 TTX bits are completed. All
teletext lines are implemented in the say way. Individual control of teletext lines is controlled by Teletext Setup Registers.
ADDRESS & DATA
RUN-IN CLOCK
TELETEXT VBI LINE
45 BYTES (360 BITS) – PAL
Figure 59. Teletext VBI Line
PROGRAMMABLE PULSE EDGES
t
SYNTXTOUT
t
PD
t
PD
10.2
m
s
TXT
ST
TXT
DEL
CVBS/Y
HSYNC
TXTREQ
TXT
DATA
t
SYNTXTOUT
= 10.2
m
s
t
= PIPELINE DELAY THROUGH ADV7170/ADV7171
TXT
DEL
= TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
Figure 60. Teletext Functionality Diagram
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